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参数资料
| 型号： | MSC8122VT8000 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 16/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP QUAD 16B 500MHZ 431FCPBGA |
| 标准包装： | 60 |
| 系列： | StarCore |
| 类型： | SC140 内核 |
| 接口： | DSI，以太网，RS-232 |
| 时钟速率： | 500MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 1.436MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 431-BFBGA，FCBGA |
| 供应商设备封装： | 431-FCPBGA（20x20） |
| 包装： | 托盘 |
| 配用： | MSC8122ADSE-ND - KIT ADVANCED DEV SYSTEM 8122 |
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Electrical Characteristics
V IH
V IL
V DDH + 17%
V DDH + 8%
V DDH
GND
GND – 0.3 V
GND – 0.7 V
Must not exceed 10% of clock period
Figure 5. Overshoot/Undershoot Voltage for V IH and V IL
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When
systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF
load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down
to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.
When calculating overall loading, also consider additional RC delay.
2.5.1
Output Buffer Impedances
Table 6. Output Buffer Impedances
System bus
Memory controller
Parallel I/O
Output Buffers
Typical Impedance ( Ω )
50
50
50
Note:
2.5.2
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3
describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8122 device:
?
?
?
?
Note:
PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table 11 for timing.
If possible, bring up the V DD and V DDH levels together. For designs with separate power supplies, bring up the V DD
levels and then the V DDH levels (see Figure 7 ).
CLKIN should start toggling at least 16 cycles (starting after V DDH reaches its nominal level) before PORESET
deassertion to guarantee correct device operation (see Figure 6 and Figure 7 ).
CLKIN must not be pulled high during V DDH power-up. CLKIN can toggle during this period.
See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power supply design
recommendations.
The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which V DD and V DDH are
raised together. Figure 7 shows a sequence in which V DDH is raised after V DD and CLKIN begins to toggle as V DDH rises.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
16
Freescale Semiconductor
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| MSC8126ADSE | 功能描述:KIT ADVANCED DEV SYSTEM 8126 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:StarCore 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
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