参数资料
型号: MSC8126ADSE
厂商: Freescale Semiconductor
文件页数: 41/48页
文件大小: 0K
描述: KIT ADVANCED DEV SYSTEM 8126
标准包装: 1
系列: StarCore
类型: DSP
适用于相关产品: MSC8126
所含物品:
相关产品: MSC8126TMP6400-ND - DSP 16BIT 400MHZ MULTI 431FCPBGA
MSC8126MP8000-ND - DSP 16BIT 500MHZ MULTI 431FCPBGA
MSC8126VT8000-ND - IC DSP QUAD 16B 500MHZ 431FCPBGA
MSC8126TVT6400-ND - IC DSP QUAD 16B 400MHZ 431FCPBGA
Hardware Design Considerations
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Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three
capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount
at least one of the capacitors directly below the MSC8126 device.
Maximum IR drop
of 15 mV at 1 A
L max = 2 cm
1.2 V
One 0.01 μF capacitor
Power supply
or
for every 3 core supply
pads.
MSC8122
Voltage Regulator
(I min = 3 A)
+
-
Bulk/Tantalum capacitors
with low ESR and ESL
Note : Use at least three capacitors.
Each capacitor must be at least 150 μ F.
High frequency capacitors
(very low ESR and ESL)
Figure 33. Core Power Supply Decoupling
Each V CC and V DD pin on the MSC8126 device should have a low-impedance path to the board power supply. Similarly, each
GND pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the
chip. The V CC power supply should have at least four 0.1 μF by-pass capacitors to ground located as closely as possible to the
four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip V CC , V DD , and GND should
be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as V CC and
GND planes.
All output pins on the MSC8126 have fast rise and fall times. PCB trace interconnection length should be minimized to
minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to
the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in
synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.
Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to
proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V CC , V DD , and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins:
V CCSYN - GND SYN . To ensure internal clock stability, filter the power to the V CCSYN input with a circuit similar to the one in
Figure 34 . For optimal noise filtering, place the circuit as close as possible to V CCSYN . The 0.01-μF capacitor should be closest
to V CCSYN , followed by the 10-μF capacitor, the 10-nH inductor, and finally the 10- Ω resistor to V DD . These traces should be
kept short and direct. Provide an extremely low impedance path to the ground plane for GND SYN . Bypass GND SYN to V CCSYN
by a 0.01-μF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of
the PCB aligned with the depopulated void on the MSC8126 located in the square defined by positions, L11, L12, L13, M11,
M12, M13, N11, N12, and N13.
V DD
10 Ω
10nH
V CCSYN
10 μF
0.01 μF
Figure 34. V CCSYN Bypass
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
41
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