参数资料
型号: MSL2161DQ-R
厂商: Atmel
文件页数: 17/28页
文件大小: 0K
描述: IC LED DRVR 16 CHAN PWM 64TQFN
产品培训模块: Industrial Panel Backlighting Driver ICs
LED Lighting Drivers
LED Driver Basics
标准包装: 2,500
系列: Adaptive SourcePower™
拓扑: 交直流离线开关,PWM
输出数: 16
内部驱动器:
类型 - 主要: 背光,通用
类型 - 次要: RGB,白色 LED
频率: 19.4MHz ~ 20.6MHz
电源电压: 10.8 V ~ 13.2 V
输出电压: 8.3V
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘
供应商设备封装: 64-TQFN(9x9)
包装: 带卷 (TR)
工作温度: -40°C ~ 105°C
Atmel LED Drivers-MSL2160/MSL2161
16-string, White and RGB LED Drivers with Adaptive Configuration,
EEPROM, and SPI/I 2 C/SMBus Serial Interface
PARAMETER
SCK Falling Edge to MISO Data Valid
SYMBOL
t VALID
CONDITIONS AND NOTES
(Note 1)
MIN
TYP
MAX
20
UNIT
ns
SCK High Time
SCK Low Time
20
20
ns
ns
MOSI, CSB, SCK Signal Rise Time
MOSI, CSB, SCK Signal Fall Time
MISO Signal Rise Time
MISO Signal Fall Time
t R(SPI)
t F(SPI)
Receiving (Note 6)
Receiving (Note 6)
C load = 10pF (Note 6)
C load = 10pF (Note 6)
5.0
5.0
20
20
ns
ns
ns
ns
PARAMETER
SYMBOL
CONDITIONS AND NOTES
MIN
TYP
MAX
UNIT
I2C TIMING CHARACTERISTICS, MSL2161
SCL Clock Frequency
1/t SCL
I2CTOEN = 0 (Note 2)
0
1
MHz
Bus Timeout Period
t timeout
f OSC = 20MHz, T A = 25°C
f OSC = 16MHz to 23MHz
29
30
600,000 / f OSC
31
ms
s
STOP to START Condition Bus Free Time
Repeated START condition Hold Time
Repeated START condition Setup Time
STOP Condition Setup Time
SDA Data Hold Time
t BUF
t HD:STA
t SU:STA
t SU:STOP
t HD:DAT
0.5
0.26
0.26
0.26
0
μs
μs
μs
μs
ns
SDA Data Valid Acknowledge Time
SDA Data Valid Time
SDA Data Set-Up Time
SCL Clock Low Period
SCL Clock High Period
SDA, SCL Fall Time
SDA, SCL Rise Time
SDA, SCL Input Suppression Filter Period
t VD:ACK
t VD:DAT
t SU:DAT
t LOW
t HIGH
t f
t r
t SP
(Note 3)
(Note 4)
(Note 1, Note 5, Note 6)
(Note 2, Note 7)
0.05
0.05
100
0.5
0.26
50
0.45
0.45
120
120
μs
μs
ns
μs
μs
ns
ns
ns
Note 1. Guaranteed by design, not production tested.
Note 2. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for
time-out. Disable bus timeout via the Fault Enable register 0x03[D6].
Note 3. t V D:AC K = SCL LOW to SDA (out) LOW acknowledge time.
Note 4. t V D:DAT = minimum SDA output data-valid time following SCL LOW transition.
Note 5. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state.
Note 6. The maximum SDA, SCL and MOSI rise times are 300ns. This allows series protection resistors to be connected between these inputs and
the bus lines without exceeding the maximum allowable rise time. The maximum SDA and MISO fall time is 250ns.
Note 7. The MSL2161 includes input filters on SDA, SCL and ADDR inputs that suppress noise less than 50ns.
Note 8. The GSC input frequency multiplied by (GSCMUL + 1) should not exceed 2.5MHz.
Note 9. When PWMDIRECT = 1 and PHDLYEN = 1 (external PWM with auto phase shift enabled), PWM duty cycles at 0% and 100% are guaranteed,
other duty cycles require minimum on or off time of one full internal oscillator clock cycle and frequency greater than (f OSC /10 6 )Hz.
Atmel LED Drivers-MSL2160/MSL2161
17
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MSL2164-DUR 功能描述:LED照明驱动器 16-String LED Driver Mult-PWM Modes 3FO RoHS:否 制造商:STMicroelectronics 输入电压:11.5 V to 23 V 工作频率: 最大电源电流:1.7 mA 输出电流: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:SO-16N
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