参数资料
型号: MSL3162BT
厂商: Atmel
文件页数: 11/20页
文件大小: 0K
描述: IC LED DRIVER 16 STRING
产品培训模块: Industrial Panel Backlighting Driver ICs
LED Lighting Drivers
LED Driver Basics
标准包装: 2,500
系列: Adaptive SourcePower™
拓扑: 交直流离线开关,PWM
输出数: 16
内部驱动器:
类型 - 主要: 背光,通用
类型 - 次要: RGB,白色 LED
频率: 18MHz ~ 22MHz
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN(6x6)
包装: 管件
工作温度: -40°C ~ 85°C
Atmel LED Driver-MSL3162
16-string, RGB and White LED Drivers with Adaptive
Power Control and 1MHz I 2 C/SMBus Serial Interface
PARAMETER
GSC frequency
CONDITIONS AND NOTES
MIN
0
TYP
MAX
5
UNIT
MHz
High and low time PHI, GSC
40
ns
PWM frequency
PWM duty cycle
PHI DLL lock cycles
(Note 10)
20
0.5
4
50000
100
Hz
%
PHI
cycles
PARAMETER
SYMBOL
CONDITIONS AND NOTES
MIN
TYP
MAX
UNIT
I2C SWITCHING CHARACTERISTICS
SCL clock frequency
1/t SCL
Bus timeout disabled (Note 2)
0
1000
kHz
Bus timeout period
t TIMEOUT
OSCTRL = 0x04 (f OSC =20MHz); T A =25°C
OSCTRL = 0x00 to 0x07; f OSC =16 to 23MHz
27
30
600000 / f OSC
33
ms
STOP to START condition bus
free time
Repeated START condition hold
time
Repeated START condition setup
time
STOP condition setup time
SDA data hold time
t BUF
t HD:STA
t SU:STA
t SU:STOP
t HD:DAT
0.5
0.26
0.26
0.26
5
μs
μs
μs
μs
ns
SDA data valid acknowledge time
SDA data valid time
SDA data set-up time
SCL clock low period
SCL clock high period
SDA, SCL fall time
SDA, SCL rise time
SDA, SCL input suppression filter
period
t VD:ACK
t VD:DAT
t SU:DAT
t LOW
t HIGH
t F
t R
t SP
(Note 3)
(Note 4)
(Note 5, Note 6)
(Note 7, Note 10)
0.05
0.05
100
0.5
0.26
50
0.55
0.55
120
120
μs
μs
ns
μs
μs
ns
ns
ns
Note 1. All parameters are tested at T A =25°C unless otherwise noted. Specifications at temperature are guaranteed by design
Note 2. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA
or SCL is held low for t TIMEOUT . Disable bus timeout feature for DC operation
Note 3. t VD:ACK = SCL low to SDA (out) low acknowledge time
Note 4. t VD:DAT = minimum SDA output data-valid time following SCL low transition
Note 5. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state
Note 6. The maximum SDA and SCL rise times are 300ns. The maximum SDA fall time is 250ns. This allows series protection resistors to be
connected between SDA and SCL inputs and the SDA/SCL bus lines without exceeding the maximum allowable rise time
Note 7. MSL3162 includes input filters on SDA, SCL, AD0, and AD1 inputs that suppress noise less than 50ns
Note 8. Subject to thermal dissipation characteristics of the device
Note 9. When mounted according to JEDEC, JEP149, and JESD51-12 for a two-layer PCB, θ JA = 18.6°C/W and θ JC = 1.4°C/W
Note 10. Guaranteed by design and characterization. Not production tested
Atmel LED Driver-MSL3162
11
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