参数资料
型号: MSLB9082BCB
厂商: Atmel
文件页数: 6/20页
文件大小: 0K
描述: LED BCKLT DVR MOD 8CH I2C QFN
标准包装: 1
输出及类型: 8,非隔离
特点: 可调光,I²C 接口
已供物品:
已用 IC / 零件: MSL3162
PARAMETER
CONDITIONS AND NOTES
MIN
TYP
MAX
UNIT
AC ELECTRICAL CHARACTERISTICS
PWM input frequency
20
kHz
PARAMETER
CONDITIONS AND NOTES
MIN
TYP
MAX
UNIT
I2C SWITCHING CHARACTERISTICS
SCL clock frequency
Bus timeout
Bus free time between a STOP and
START condition
Hold time for a repeated START condition
Set-up time for a repeated START condition
Set-up time for STOP condition
Data hold time
I 2 C timeout disabled (Note 1)
0.5
0.26
0.26
0.26
10
25
1000
kHz
ms
μs
μs
μs
μs
ns
Data valid acknowledge time
Data valid time
Data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
Fall time of SDA and SCL signals
Rise time of both SDA and SCL signals
Pulse width of spikes that must be
suppressed by the input filter
SDA, SCL, AD0 input capacitance
(Note 2)
(Note 3)
(note 4,5)
(Note 6)
0.05
0.05
100
0.5
0.26
50
10
0.45
0.45
120
120
μs
μs
ns
μs
μs
ns
ns
ns
pF
Note 1. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for
25ms. Disable bus timeout feature for DC operation.
Note 2. Time for acknowledge signal from SCL low to SDA (out) low.
Note 3. Minimum time for SDA data out to be valid following SCL low.
Note 4. A master device must internally provide a hold time of at least 300ns for the SDA signal (refer to the V IL of the SCL signal) in order to
bridge the undefined region of SCL falling edge.
Note 5. The maximum fall times for the SDA and SCL bus lines are specified at 300ns. The maximum fall time for the SDA output stage is specified
at 250ns. This allows series protection resistors to be connected between SDA and SCL and the SDA/SCL bus lines without exceeding the
maximum specified fall time.
Note 6. Input filters on the SDA, SCL, and AD0 inputs suppress noise less than 50ns
6
Atmel LED Driver-MSLB9082
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