参数资料
型号: MSLB9082ECB
厂商: Atmel
文件页数: 13/20页
文件大小: 0K
描述: LED BCKLT DVR MOD 8CH I2C QFN
标准包装: 1
输出及类型: 8,非隔离
特点: 可调光,I²C 接口
已供物品:
已用 IC / 零件: MSL3162
Atmel LED Driver-MSLB9082
LED Backlight Driver Module
Compact, 8-channel, 20W LED Driver Board with I 2 C Interface
Setting the Internal PWM Dimming
Frequency and Duty Cycle
The MSL3162 internally generates the PWM dimming
duty cycle and frequency. The PWM dimming
frequency is programmable, as are the PWM duty cycle
and phasing between LED strings.
Setting the PWM Dimming Frequency
The PWM frequency (PHI frequency) is internally set
by the IPHIGEN register. This 16-bit number sets the
divider ratio from an internal 2.5MHz clock. Therefore,
the PWM frequency is:
For D MAX >1, the maximum duty cycle is 100%.
Setting the LED PWM Dimming Duty Cycle
The MSL3162 allows each LED string to operate at
different duty cycles and phases. The per-string PWM
dimming duty cycle for any LED string is set by the
PWM n register, where n is the LED string number.
The MSL3162 also offers PWM dimming of all strings
simultaneously through the global intensity (GINT)
register. Each string PWM on time is set by the eight
most-significant bits of the product of the PWMn
and GINT registers, multiplied by the GSC period:
t ON_PWMn = ? ?
? ? * ?
? ? PWMn * GINT ?
?
? ?
f PWM =
2 . 5 MHz
IPHIGEN
? 1
? f GSC
64 ?
t ON_PWMn = ?
? IGSCGEN ? 1 ? ? PWMn * GINT ?
? * ? ?
IPHIGEN =
2 . 5 MHz
f PWM
For high dimming accuracy, keep the PWM dimming
frequency below 10kHz. To set the PWM frequency,
program the IPHIGEN register between 38Hz and
10kHz per the equation:
,
where IPHIGEN ranges between 250 (0x00FA) and
65535 (0xFFFF)
For full PWM dimming resolution, make sure that the
ratio between the IGSCGEN register and IPHIGEN
register is 32. See Setting the PWM Dimming
Resolution for more details.
Setting the PWM Dimming Resolution
The MSL3162 uses the IPHIGEN register to set the
PWM dimming frequency, and it uses the IGSCGEN
register to set the PWM dimming resolution (GSC
frequency). The MSL3162 internally counts using the
frequency set by the IGSCGEN register to set the PWM
duty and phasing. Full PWM dimming is achieved if the
ratio of IGSCGEN to IPHIGEN is less than 32. If the ratio
? 20 MHz ? ? 64 ?
where PWMn ranges from 0 to 256 (0xFF) and GINT
ranges from 0 to 64 (0x3F).
Setting the LED PWM Dimming Phasing
Each LED string’s PWM dimming occurs with
independent phasing. This is useful to force phase
shifted PWM dimming, which reduces the transient load
on the DC-DC converter, improving performance.
The phase of each LED string is set by PHDLY n ,
where n is the LED string number. The MSL3162
counts GSC pulses to determine the on-time delay
from the beginning of each PHI frame. For example,
if PHDLY0 is set to 0x00, the LED string 0 on time
starts at the beginning of a PHI frame. If PHDLY0 is
set to 0x40, the LED string 0 on time begins at 64
(0x40) GSC pulses after the beginning of a PHI frame.
t PHDLYn = ? ?
? ? * PHDLYn
is greater than 32, then the maximum achievable duty
cycle is:
? 1
? f GSC
?
?
D MAX = 32 × ?
? IGSCGEN ? 1 ?
? IPHIGEN ?
t PHDLYn = ?
? * PHDLYn
Atmel LED Driver-MSLB9082
?
? IGSCGEN ? 1 ?
? 20 MHz ?
13
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