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参数资料
| 型号： | MSM512100 |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 2M×1 Dynamic RAM(2M×1动态RAM) |
| 中文描述： | 200万× 1动态RAM（2米× 1动态内存） |
| 文件页数： | 8/16页 |
| 文件大小： | 235K |
| 代理商： | MSM512100 |
8/16
Semiconductor
MSM512100/L
Notes:
1. A start-up delay of 200
μ
s is required after power-up, followed by a minimum of
eight initialization cycles (
RAS
-only refresh or
CAS
before
RAS
refresh) before
proper device operation is achieved.
2. The AC characteristics assume t
T
= 5 ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals.
Transition times (t
T
) are measured between V
IH
and V
IL
.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified
t
RCD
(Max.) limit, then the access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified
t
RAD
(Max.) limit, then the access time is controlled by t
AA
.
7. t
OFF
(Max.) defines the time at which the output achieves the open circuit condition and
is not referenced to output voltage levels.
8. t
RCH
or t
RRH
must be satisfied for a read cycle.
9. t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If t
WCS
≥
t
WCS
(Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t
CWD
≥
t
CWD
(Min.) , t
RWD
≥
t
RWD
(Min.),
t
AWD
≥
t
AWD
(Min.) and t
CPWD
≥
t
CPWD
(Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the
CAS
leading edge in an early write cycle, and
to the
WE
leading edge in an
OE
control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a
WE
and
CAS
before
RAS
refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is a 4-bit parallel test function. RA10 and
CA0 are not used. In a read cycle, if all internal bits are equal, the data output pin
will indicate a high level. If any internal bits are not equal, the data output pin will
indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a
RAS
-only refresh cycle or a
CAS
before
RAS
refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specified value. These parameters should be specified in test mode cycle by adding the
above value to the specified value in this data sheet.
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PDF描述 |
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| MSM512800A | 262,144-Word x 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
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相关代理商/技术参数 |
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|---|---|
| MSM512100-60SJ | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:2,097,152-Word X 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| MSM512100-70SJ | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:2,097,152-Word X 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| MSM512100-80SJ | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:2,097,152-Word X 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| MSM512100J | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:2,097,152-Word X 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| MSM512100L-60SJ | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:2,097,152-Word X 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
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