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参数资料
| 型号： | MSM514256CL |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 256K×4 Dynamic RAM(256K×4动态RAM) |
| 中文描述： | 256K × 4动态RAM（256K × 4动态内存） |
| 文件页数： | 8/17页 |
| 文件大小： | 257K |
| 代理商： | MSM514256CL |
8/17
Semiconductor
MSM514256C/CL
Notes:
1. A start-up delay of 100
μ
s is required after power-up, followed by a minimum of eight
initialization cycles (
RAS
-only refresh or
CAS
before
RAS
refresh) before proper device
operation is achieved.
2. The AC characteristics assume t
T
= 5 ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals.
Transition times (t
T
) are measured between V
IH
and V
IL
.
4. V
IH
= 3.0 V and V
IL
= 0.0 V are reference levels for measuring input timing signals
(speed ranks 45 and 50).
5. V
IH
= 2.4 V and V
IL
= 0.8 V are reference levels for measuring input timing signals
(speed ranks 60 and 70).
6. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
7. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified
t
RCD
(Max.) limit, then the access time is controlled by t
CAC
.
8. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified
t
RAD
(Max.) limit, then the access time is controlled by t
AA
.
9. t
OFF
(Max.) and t
OEZ
(Max.) define the time at which the output achieves the open
circuit condition and are not referenced to output voltage levels.
10. t
RCH
or t
RRH
must be satisfied for a read cycle.
11. t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If t
WCS
≥
t
WCS
(Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t
CWD
≥
t
CWD
(Min.) , t
RWD
≥
t
RWD
(Min.),
t
AWD
≥
t
AWD
(Min.) and t
CPWD
≥
t
CPWD
(Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
12. These parameters are referenced to the
CAS
leading edge in an early write cycle, and
to the
WE
leading edge in an
OE
control write cycle, or a read modify write cycle.
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