参数资料
型号: MSM514262-70JS
厂商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 262,144-Word x 4-Bit Multiport DRAM
中文描述: 262,144字× 4位多端口内存
文件页数: 9/45页
文件大小: 507K
代理商: MSM514262-70JS
Semiconductor
MSM514262
9/45
Notes:
1. These parameters depend on output loading. Specified values are obtained with
the output open.
2. These parameters are masured at minimum cycle test.
3. I
CC2
(Max.) are mesured under the condition of TTL input level.
4. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring timing of input signals.
Also, transition times are measured between V
IH
and V
IL
.
5. An initial pause of 200
m
s is required after power-up followed by any 8
RAS
cycles
(
DT
/
OE
“high”) and any 8 SC cycles before proper divice operation is achieved. In
the case of using an internal refresh counter, a minimum of 8
CAS
before
RAS
initialization cycles in stead of 8
RAS
cycles are required.
6. AC measurements assume t
T
= 5 ns.
7. RAM port outputs are mesured with a load equivalent to 1 TTL load and 100 pF.
Output reference levels are V
OH
/V
OL
= 2.4 V/0.8 V.
8. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.
Output reference levels are V
OH
/V
OL
= 2.0 V/0.8 V.
9. t
OFF
(Max.), t
OEZ
(Max.), t
SDZ
(Max.) and t
SEZ
(Max.) difine the time at which the
outputs achieve the open circuit condition and are not reference to output voltage
levels.
10. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
11. These parameters are referenced to
CAS
leading edge of early write cycles and to
WB
/
WE
leading edge in
OE
controlled write cycles and read modify write cycles.
12. t
WCS
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only.
If t
WCS
t
WCS
(Min.), the cycle is an early write cycle, and the data out pin will
remain open circuit (high impedance) throughout the entire cycle : If t
RWD
t
RWD
(Min.), t
CWD
t
CWD
(Min.) and t
AWD
t
AWD
(Min.) the cycle is a read-write cycle
and the data out will contain data read from the selected cell : If neither of the above
sets of conditions is satisfied, the condition of the data out (at access time) is
indterminate.
13. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met. t
RCD
(Max.) is specified as a reference point only : If t
RCD
is greater than the specified t
RCD
(Max.) limit, then access time is controlled by t
CAC
.
14. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met. t
RAD
(Max.) is specified as a reference point only : If t
RAD
is greater than the specified t
RAD
(Max.) limit, then access time is controlled by t
AA
.
15. Input levels at the AC parameter measurement are 3.0 V/0 V.
16. Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permenent damege to the device.
17. All voltages are referenced to V
SS
.
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