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参数资料
| 型号： | MSM519205-80SJ |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 4,194,304-Word X 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| 中文描述： | 4194304字× 2位动态随机存储器：快速页面模式型与江户 |
| 文件页数： | 8/18页 |
| 文件大小： | 658K |
| 代理商： | MSM519205-80SJ |
8/18
Semiconductor
MSM519205
Notes:
1. A start-up delay of 200
μ
s is required after power-up, followed by a minimum of eight
initialization cycles (
RAS
-only refresh or
CAS
before
RAS
refresh) before proper device
operation is achieved.
2. The AC characteristics assume t
T
= 5 ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals.
Transition times (t
T
) are measured between V
IH
and V
IL
.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified
t
RCD
(Max.) limit, then the access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified
t
RAD
(Max.) limit, then the access time is controlled by t
AA
.
7. t
CEZ
(Max.), t
REZ
(Max.), t
WEZ
(Max.) and t
OEZ
(Max.) define the time at which the
output achieves the open circuit condition and are not referenced to output voltage
levels.
8. t
CEZ
and t
REZ
must be satisfied for open circuit condition.
9. t
RCH
or t
RRH
must be satisfied for a read cycle.
10. t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If t
WCS
≥
t
WCS
(Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t
CWD
≥
t
CWD
(Min.) , t
RWD
≥
t
RWD
(Min.),
t
AWD
≥
t
AWD
(Min.) and t
CPWD
≥
t
CPWD
(Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the
CAS
leading edge in an early write cycle, and
to the
WE
leading edge in an
OE
control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a
WE
and
CAS
before
RAS
refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated. In a test mode
CA0, CA1 and CA10 are not used and each DQ pin now accesses 8-bit locations. Since
all 2 DQ pins are used, a total of 16 data bits can be written in parallel into the memory
array. In a read cycle, if 8 data bits are equal, the DQ pin will indicate a high level. If the
8 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared
and the memory device returned to its normal operating state by performing a
RAS
-
only refresh cycle or a
CAS
before
RAS
refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specified value. These parameters should be specified in test mode cycle by adding the
above value to the specified value in this data sheet.
14. These parameters are determined by the falling edge of either
CAS1
or
CAS2
,
whichever is earlier.
15. These parameters are determined by the rising edge of either
CAS1
or
CAS2
,
whichever is later.
16. t
CWL
should be satisfied by both
CAS1
and
CAS2
.
17. t
CP
is determined by the time both
CAS1
and
CAS2
are high.
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相关代理商/技术参数 |
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|---|---|
| MSM519205-80TS-K | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:4,194,304-Word X 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM51C256 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:262,144 WORD X 1-BITS DYNAMIC RAM |
| MSM51C256-10 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:262,144 WORD X 1-BITS DYNAMIC RAM |
| MSM51C256-12 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:262,144 WORD X 1-BITS DYNAMIC RAM |
| MSM51C256-8 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:262,144 WORD X 1-BITS DYNAMIC RAM |
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