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参数资料
| 型号： | MSM62X42BRS |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDIP18 |
| 封装： | 0.300 INCH, PLASTIC, DIP-18 |
| 文件页数： | 6/27页 |
| 文件大小： | 210K |
| 代理商： | MSM62X42BRS |
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Semiconductor
MSM62X42B
54
c) IRQ FLAG (D2) (Interrupt Request FLAG)
This status bit corresponds to "L" or "OPEN" of the STD.P output pin. When STD.P="L", then
this bit=1 and when STD.P=OPEN, then this bit=0.
This bit indicates that an interrupt has occurred to a microcomputer mainly. When D0 of
register CE(MASK)=0, then the STD.P output changes from OPEN to "L" and this bit changes
from "0" to "1" according to the timing set by D3(t1) and D2(t0) of the register CE.
When D1(ITRPT/STND) of the register CE is 1 (interrupt mode), the "1" of this bit (the "L" of
the STD.P output) remains until "0" is written into this bit. When this bit is "1" and timing
for a new interrupt occurs, the new interrupt is ignored. When D1(ITRPT/STND)=0 (fixed
cycle output waveform mode), the "1" of this bit (the "L" of the STD.P output) keeps "1" until
either "0" is written to this bit, or this bit automatically returns after 7.8125ms. The using
examples for the alarm are shown in the item "Set STD.P at alarm mode of APPLICATION
NOTE".
d) 30 sec. ADJ bit (30 sec. ADJUST)
This is a bit for 30-second adjustment. When "1" is written into this bit, the compensation for
30 seconds is performed. The duration for 125
s from the time written into this bit should
not be read from or written into registeres S1 ~ W (addresses 0 ~ C).
This bit for 125
s from the time written into this bit is kept in "1" and then it will automatically
return to "0". After "1" is written into this bit, the registeres S0 ~ W (addresses 0 ~ C) are
operationed with confirmation of automatical return to "0" of this bit.
CE REGISTER (Control E Register)
a) MASK (D0)
This bit controls the STD.P output. When this bit=1, then the STD.P output becomes open.
When this bit=0, then the STD.P output=output mode. The relationship between the MASK
bit and STD.P output is shown as follows.
In the case of interrupt mode (ITRPT/STND bit="1")
In the case of fixed cycle output waveform mode (ITRPT/STND bit="0")
"1"
"0"
MASK BIT
STD.P OUTPUT
WRITE “0” INTO IRQ FLAG BIT
"INTERRUPT" TIMING
LOW LEVEL
OPEN
"INTERRUPT" DOES
NOT OCCUR BECAUSE
MASK BIT IS "1"
IN TRT/STND BIT = "1"
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MSM62X42BRS-A | 制造商:ROHM Semiconductor 功能描述: |
| MSM62X42BRS-B | 制造商:ROHM Semiconductor 功能描述: |
| MSM6307 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:D2B TRANSCEIVER LSI |
| MSM6307GS-VK | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:D2B TRANSCEIVER LSI |
| MSM6307RS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:D2B TRANSCEIVER LSI |
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