参数资料
型号: MSM6636GS-VK
厂商: OKI ELECTRIC INDUSTRY CO LTD
元件分类: 微控制器/微处理器
英文描述: 1 CHANNEL(S), 41.6K bps, LOCAL AREA NETWORK CONTROLLER, PDSO24
封装: 0.430 INCH, 1.27 PITCH, PLASTIC, SOP-24
文件页数: 56/70页
文件大小: 1115K
代理商: MSM6636GS-VK
MSM6636/6636B User’s Manual
Overview
1 – 1
1. OVERVIEW
1.1 Overview
The MSM6636/6636B are transmission controllers for automotive LAN that conform to data communication
protocol SAE-J1850. These LSI devices can realize a data bus topology bus LAN system that employs the
PWM bit encoding method (41.6 kbps). In addition to a protocol control circuit, the MSM6636/6636B have an
oscillation circuit, host CPU interface (clock synchronous serial/UART)*, a transmit/receive buffer, and a bus
receiver circuit, thereby decreasing the load on the host CPU.
*In MSM6636B, the host CPU is accessed through parallel interface.
1.2 Features
Conforms to SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issued August 12,
1991)
CSMA/CD (carrier-sense multiple access with collision detection)
Internal transmit buffer (1 frame) and receive buffer (2 frames)
Bit encoding: PWM (pulse width modulation)
Transmission speed: 41.6 kbps
Multiaddress setting: 1 type of physical addressing and 15 types of functional addressing
Address filter function by multiaddressing (broadcasting possible)
Automatic retransmission when lost in contention or in the case of non-ACK
Supports 3 types of in-frame responses
1) Single-byte response from a single recipient
2) Multibyte response from a single recipient (with CRC code)
3) Single-byte response from multiple recipients (ID response as ACK)
Error detection by cyclic redundancy check (CRC)
Various communication error detections
Dual-wire bus abnormality detection by internal bus receiver and fault tolerant function
Host CPU interface
(1) MSM6636
Host CPU is accessed through serial interface with LSB first. Serial 4modes supported:
- Clock synchronous serial (no parity)
1)
Normal mode: 8-bit data
2)
MPC mode:
8-bit data + MPC bit (address/data select bit: 1 indicates address. 0 indicates data)
- UART (parity yes/no selectable)
3, 4) Normal mode: 1 start bit + 8-bit data + (parity) + 1 stop bit
5, 6) MPC mode:
1 start bit + 8-bit data + MPC bit + (parity) + 1 stop bit
(2) MSM6636B
Host CPU is accessed through parallel interface.
Sleep function
Low power mode with oscillator stopped (IDS Max < 50 A)
SLEEP/WAKE-UP control from host CPU; WAKE-UP via LAN bus
Package:
(1) MSM6636
18-pin plastic DIP (DIP18-P-300-2.54) (Product name: MSM6636RS)
18-pin plastic QFJ (QFJ18-P-R290-1.27) (Product name: MSM6636JS)
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6636GS-VK)
(2) MSM6636B
24-pin plastic SOP(SOP24-P-430-1.27-K) (Product name: MSM6636BGS-K)
30-pin plastic SOP(SSOP30-P-56-0.65-K) (MSM6636BGS-AK)
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