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参数资料
| 型号： | MSM6665-XX |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 显示控制器 |
| 英文描述： | 17 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC117 |
| 封装： | 6.05 X 4.98 MM, ALUMINIUM PAD, DIE-117 |
| 文件页数： | 10/32页 |
| 文件大小： | 364K |
| 代理商： | MSM6665-XX |
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OKI Semiconductor
MSM6665-xx
FEDL6665-04
Flowchart for Power-On Timing
Turn on power
Reset input
Wait for 20 clocks
5ms required; external reset input or power-on reset input
CS="H"
The device is enabled.
10 clocks at 1/17 duty
20 clocks at 1/9 duty
Clock input for initial busy clear.
SOE/D, D0="1"
Make the SO output enable, to perform busy detection.
Wait for 20 clocks
Input a wait for the SOE/D command processing. (For the processing
of each command after this, perform busy detection. *1)
BPC and BKCG
command set
Set the blink pattern and bank change mode.
LOT, I1="1", I0="1"
Set the Load Option. (Blank-code writing and blink-cancellation
are executed each time the AINC command is executed.)
AINC executed 48 times
Input the AINC command to clear the RAM data.
LOT, I1="0", I0="0"
Release the Load Option.
Input display data for initial screen
DISP, D0="1"
Display is turned on and the initial screen is displayed.
Is Input of display data for
initial screen completed?
NO
YES
Normal operation
(
)
*1
After the required commands and display data are entered, perform busy detection
based on the SO pin status. When it is confirmed that the status has been changed
from BUSY (SO="L") to NON-BUSY (SO="H"), enter the next data.
If busy detection is not performed, wait for 10 master oscillation clocks when used at
1/17 duty or for 20 master oscillation clocks when at 1/9 duty, then enter the next
data.
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| MSM6665C-02 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC117 |
| MSM6665C-XXGS-K | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP128 |
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| MSM66207-JS | 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQCC68 |
| MSM66P207-XXXGS-BK | 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64 |
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