参数资料
型号: MSM8128VI-85
元件分类: SRAM
英文描述: 128K X 8 STANDARD SRAM, 85 ns, CDXA32
封装: 0.100 INCH, VIL-32
文件页数: 5/10页
文件大小: 584K
代理商: MSM8128VI-85
MSM8128 - 70/85/10/12
Issue 4.5 : April 2001
"
AC OPERATING CONDITIONS
Read Cycle
70
85
10
12
Parameter
Symbol
min
max
min
max
min
max
min
max
Unit
Read Cycle Time
t
RC
70
-
85
-
100
-
120
-
ns
Address Access Time
t
AA
-
70
-
85
-
100
-
120
ns
Chip Select (CS1) Access Time(2)
t
ACS1
-
70
-
85
-
100
-
120
ns
Chip Select (CS2) Access Time(2)
t
ACS2
-
70
-
85
-
100
-
120
ns
Output Enable to Output Valid
t
OE
-35
-
45
-50
-
60
ns
Output Hold from Address Change
t
OH
5-
10
-
10
-
ns
Chip Selection (CS1) to Output in Low Z
t
CLZ1
10
-
10
-
10
-
10
-
ns
Chip Selection (CS2) to Output in Low Z
t
CLZ2
10
-
10
-
10
-
10
-
ns
Output Enable to Output in Low Z
t
OLZ
5-
ns
Chip Disable (CS1) to Output in High Z(3)
t
CHZ1
035035
035045
ns
Chip Disable (CS2) to Output in High Z(3)
t
CHZ2
035035
035045
ns
Output Disable to Output in High Z(3)
t
OHZ
030030
035045
ns
Write Cycle
70
85
10
12
Parameter
Symbol
min
max
min
max
min
max
min
max
Unit
Write Cycle Time
t
WC
70
-
85
-
100
-
120
-
ns
Chip Selection to End of Write
t
CW
60
-
75
-
85
-
100
-
ns
Address Valid to End of Write
t
AW
60
-
75
-
85
-
100
-
ns
Address Setup Time
t
AS
0-
ns
Write Pulse Width
t
WP
50
-
60
-
70
-
70
-
ns
Write Recovery Time (WE, CS1)
t
WR1
5-
ns
(CS2)
t
WR2
5-
ns
Write to Output in High Z
t
WHZ
030030
035040
ns
Data to Write Time Overlap
t
DW
30
-
35
-
40
-
45
-
ns
Data Hold from Write Time
t
DH
0-
ns
Output Active from End of Write
t
OW
5-
ns
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