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参数资料
| 型号： | MSM82C54-2 |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Programmable Universal Timers(可编程中断定时器,最高计数频率10MHz) |
| 中文描述： | 可编程通用定时器（可编程中断定时器，最高计数频率10MHz时） |
| 文件页数： | 12/23页 |
| 文件大小： | 162K |
| 代理商： | MSM82C54-2 |
12/23
Semiconductor
MSM82C54-2RS/GS/JS
Mode definition
Mode 0
Application: Event counter
Output operation: The output is set to “L” level by the control word setting, and kept at “L”
level until the counter value becomes 0.
Gate function: “H” level validates the count operation, and “L” level invalidates it. The gate
does not affect the output.
Count value load timing: after the control word and initial count value are written, the count
value is loaded to the CE at the falling edge of the next clock pulse. The first clock pulse does
not cause the count value to be decremented. In other words, if the initial count value is N,
the output is not set to “H” level until the input of (N+1) the clock pulse after the initial count
value writing.
Count value writing during counting:
The count value is loaded in the CE at the falling edge of the next clock, and counting with the
new count value continues. The operation for 2-byte count is as follows:
1) The counting operation is suspended when the first byte is written. The output is
immediately set to “L” level. (no clock pulse is required.)
2) After the second byte is written, the new count value is loaded to the CE at the falling edge
of the next clock.
For the output to go to “H” level again, N+1 clock pulse are necessary after new count value
N is written.
Count value writing when the gate signal is “L” level:
The count value is also loaded to the CE at the falling edge of the next clock pulse in this case.
When the gate signal is set to “H” level, the output is set to “H” level after the lapse of N clock
pulses. Since the count value is already loaded in the CE, no clock pulse for loading in the CE
is necessary.
Mode 1
Application: Digital one-shot
Output operation: The output is set to “H” level by the control word setting. It is set to “L”
level at the falling edge of the clock succeeding the gate trigger, and kept at “L” level until the
counter value becomes 0. Once the output is set to “H” level, it is kept at “H” level until the
clock pulse succeeding the next trigger pulse.
Count value load timing:
After the control word and initial count value are written, the count value is loaded to the CE
at the falling edge of the clock pulse succeeding the gate trigger and set the output to “L” level.
The one-shot pulse starts in this way. If the initial count value is N, the one-shot pulse interval
equals N clock pulses. The one-shot pulse is not repetitive.
Gate function: The gate signal setting to “L” level after the gate trigger does not affect the
output. When it is set to “H” level again from “L” level, gate retriggering occurs, the CR count
value is loaded again, and counting continues.
Count value writing during counting
It does not affect the one-shot pulse being counted until retriggering occurs.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MSM82C54-2GS | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:CMOS PROGRAMMABLE INTERVAL TIMER |
| MSM82C54-2J3 | 制造商:OKI Semiconductor 功能描述:CPU I/OS EOL311208 制造商:ROHM Semiconductor 功能描述: |
| MSM82C54-2JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM82C54-2JSDR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM82C54-2R3 | 制造商:OKI Semiconductor 功能描述:PROG'ABLE PERIPHERAL INTERFACE EOL211209 |
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