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参数资料
| 型号： | MSM82C84A-2RS |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 8 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP18 |
| 封装： | 0.300 INCH, 2.54 MM PITCH, PLASTIC, DIP-18 |
| 文件页数： | 2/18页 |
| 文件大小： | 164K |
| 代理商： | MSM82C84A-2RS |
10/18
Semiconductor
MSM82C84A-2RS/GS/JS
(4) Ready Circuit
The READY signal generator circuit can be set to synchronization mode by ASYNC.
(i)
When ASYNC is at low level
The RDY input is output as the READY signal by double synchronization.
The high-level RDY input is synchronized once by the rising edge of the CLK of the first
stage flip-flop (F1 in the circuit diagram), and then synchronized again by the falling
edge of the CLK of the next stage flip-flop (F2 in the circuit diagram), resulting in output
of a high-level READY output signal (see diagram below).
The low-level RDY input is synchronized directly by the falling-edge of the CLK of the
next stage flip-flop, resulting in output of a low-level READY output signal (see
diagram below).
(ii) When ASYNC is at high level
The RDY input is output as the READY signal by single synchronization.
Both low-level and high-level RDY inputs are synchronized by the falling edge of the
CLK of the next stage flip-flop, resulting output of respective low-level and high-level
READY output signals (see diagram below).
CLK
RDY
READY
CLK
RDY
READY
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