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参数资料
| 型号： | MSM832TM-12 |
| 元件分类： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 120 ns, CDIP28 |
| 封装： | SKINNY, DIP-28 |
| 文件页数： | 1/10页 |
| 文件大小： | 139K |
| 代理商： | MSM832TM-12 |
MSM832 - 12/15
ISSUE 4.2 : November 1998
1
32K x 8 SRAM
MSM832 - 12/15
Issue 4.2 : November 1998
31
W
E
32
Vc
c
15
D
2
16
G
N
D
4
A
7
1
NC
2
A
1
4
3
A
1
2
3
0
A
13
J,W
PACKAGE
TOP VIEW
A6
5
A5
6
A4
7
A3
8
A2
9
A1 10
A0 11
NC 12
D0 13
27 A11
26 NC
25 OE
24 A10
23 CS
22 D7
21 D6
28 A9
29 A8
20
D
5
17
N
C
18
D
3
19
D
4
14
D
1
Memory Array
512 X 512
Row
Decoder
X
Address
Buffer
I/O
Buffer
Column I/O
Column Decoder
Y Address Buffer
A3
A4
A5
A6
A7
A8
A12
A13
A14
D0
D7
CS
WE
OE
A0
A1
A2
A9
A1
0
A1
1
Description
The MSM832 is a Static RAM organised as 32K x
8 available with access times of 120 or 150 ns.
The device is available in five ceramic package
options including the high denisty VIL package.
It features completely static operation with a low
power standby mode and is 3.0V battery back-up
compatible. It is directly TTL compatible and has
common data inputs and outputs.
The device may be screened in accordance with
MIL-STD-883.
32,768 x 8 CMOS Static RAM
Features
Access Times of 120/150 ns.
JEDEC Standard footprint.
Low Power Operation : 385 mW (max)
Low Power Standby : 1.1 mW (max) -L version.
Low Voltage Data Retention.
Directly TTL compatible.
Completely Static Operation.
Pin Functions
A0-A14
Address inputs
D0-7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
V
CC
Power(+5V)
GND
Ground
Pin Definitions
Block Diagram
Package Details
Pin Count
Description
Package Type
28
0.1" Vertical-in-Line (VILTM)V
28
0.3" Dual-in-line (SKINNY DIP)
T
28
0.6"Dual-in-Line (DIP)
S
32
J-Leaded Chip Carrier (JLCC)
J
32
Leadless Chip Carrier (LCC)
W
A5
A4
A6
A3
A7
A12
A14
A2
A1
A0
GND
D2
D1
D0
26
25
27
24
28
23
22
21
17
18
19
20
16
15
1
7
8
6
9
5
4
3
2
10
11
12
14
13
TOPVIEW
PACKAGE
V,T,S
VCC
A9
A11
A8
OE
A13
A10
CS
D7
D3
D4
D5
D6
WE
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
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