参数资料
型号: MSP430F1222IPW
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PDSO28
封装: PLASTIC, TSSOP-28
文件页数: 19/53页
文件大小: 1198K
代理商: MSP430F1222IPW
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D JANUARY 2002 REVISED AUGUST 2004
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
10-bit ADC, built-in reference
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Positive built-in reference
REF2_5V = 1 for 2.5 V
IVREF+ ≤ IVREF+max
VCC = 3 V
2.35
2.5
2.65
VREF+
Positive built-in reference
voltage output
REF2_5V = 0 for 1.5 V
IVREF+ ≤ IVREF+max
VCC =
2.2 V/3 V
1.41
1.5
1.59
V
REF2_5V = 0, IVREF+ ≤ 1mA
2.2
VCC(min)
VCC minimum voltage,
Positive built-in reference
REF2_5V = 1, IVREF+ ≤ 0.5mA
VREF+ + 0.15
V
VCC(min)
Positive built-in reference
active
REF2_5V = 1, IVREF+ ≤ 1mA
VREF+ + 0.15
V
Load current out of VREF+
VCC = 2.2 V
±0.5
IVREF+
Load current out of VREF+
terminal
VCC = 3 V
±1
mA
IVREF+ = 500 A +/ 100 A
VCC = 2.2 V
±2
Load-current regulation
Analog input voltage ~0.75 V;
REF2_5V = 0
VCC = 3 V
±2
LSB
IL(VREF)+
Load-current regulation
VREF+ terminal
IVREF+ = 500 A ± 100 A
Analog input voltage ~1.25 V;
REF2_5V = 1
VCC = 3 V
±2
LSB
Load current regulation
IVREF+ =100 A → 900 A,
ADC10SR = 0
400
tDL(VREF) +
Load current regulation
VREF+ terminal
VCC=3 V, Ax ~0.5 x VREF+
Error of conversion result
≤ 1 LSB
ADC10SR = 1
2000
ns
CVREF+
Capacitance at pin VREF+
(see Note 1)
REFON =1, IVREF+ ≤±1 mA
VCC =
2.2 V/3 V
100
pF
TREF+
Temperature coefficient of
built-in reference
IVREF+ is a constant in the range of
0 mA
≤ IVREF+ ≤ 1 mA
VCC =
2.2 V/3 V
±100 ppm/°C
Settle time of internal
IVREF+ = 0.5 mA,VREF+ = 1.5 V, VCC = 3.6 V,
REFON = 0
→ 1
30
tREFON
reference voltage and
VREF+
IVREF+ = 0.5 mA, VREF+ = 1.5 V,
ADC10SR = 0
0.8
s
VREF+
(see Note 2)
IVREF+ = 0.5 mA, VREF+ = 1.5 V,
VCC = 2.2 V, REFON = 1
ADC10SR = 1
2.5
Not production tested, limits characterized
Not production tested, limits verified by design
NOTES:
1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT=1),
must be limited; the reference buffer may become unstable otherwise.
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
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