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参数资料
型号： MSP430F168IRTD
厂商： TEXAS INSTRUMENTS INC
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQCC64
封装： PLASTIC, QFN-64
文件页数： 3/73页
文件大小： 1442K
代理商： MSP430F168IRTD
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368E OCTOBER 2002 REVISED AUGUST 2006
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
Watchdog
Flash memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 & 3)
OFIFG (see Notes 1 & 3)
ACCVIFG (see Notes 1 & 3)
(Non)maskable
0FFFCh
14
Timer_B7 (see Note 5)
TBCCR0 CCIFG
(see Note 2)
Maskable
0FFFAh
13
Timer_B7 (see Note 5)
TBCCR1 to TBCCR6
CCIFGs, TBIFG
(see Notes 1 & 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog timer
WDTIFG
Maskable
0FFF4h
10
USART0 receive
URXIFG0
Maskable
0FFF2h
9
USART0 transmit
I2C transmit/receive/others
UTXIFG0
I2CIFG (see Note 4)
Maskable
0FFF0h
8
ADC12
ADC12IFG
(see Notes 1 & 2)
Maskable
0FFEEh
7
Timer_A3
TACCR0 CCIFG
(see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 & 2)
Maskable
0FFEAh
5
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 & 2)
Maskable
0FFE8h
4
USART1 receive
URXIFG1
Maskable
0FFE6h
3
USART1 transmit
UTXIFG1
Maskable
0FFE4h
2
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7
(see Notes 1 & 2)
Maskable
0FFE2h
1
DAC12
DMA
DAC12_0IFG,
DAC12_1IFG
DMA0IFG, DMA1IFG,
DMA2IFG (see Notes 1 & 2)
Maskable
0FFE0h
0, lowest
NOTES:
1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. I2C interrupt flags located in the module
5. Timer_B7 in MSP430x16x/161x family has 7 CCRs; Timer_B3 in MSP430x15x family has 3 CCRs; in Timer_B3 there are only
interrupt flags TBCCR0, 1 and 2 CCIFGs and the interrupt-enable bits TBCCR0, 1 and 2 CCIEs.
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