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参数资料
| 型号： | MSP430F2410TRGC |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, QCC64 |
| 封装： | PLASTIC, QFN-64 |
| 文件页数： | 58/91页 |
| 文件大小： | 1246K |
| 代理商： | MSP430F2410TRGC |
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MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547H
– JUNE 2007 – REVISED AUGUST 2011
12-bit ADC, Power Supply and Input Range Conditions
(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
AVCC and DVCC are connected together
AVCC
Analog supply voltage
AVSS and DVSS are connected together
2.2
3.6
V
V(AVSS) = V(DVSS) = 0 V
All P6.0/A0 to P6.7/A7 terminals, Analog inputs
Analog input voltage
selected in ADC12MCTLx register,
V(P6.x/Ax)
0
VAVCC
V
range(2)
P6Sel.x = 1, 0
≤ × ≤ 7,
V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
fADC12CLK = 5 MHz,
2.2 V
0.65
0.8
Operating supply current
IADC12
ADC12ON = 1, REFON = 0,
mA
into AVCC terminal
(3)
3 V
0.8
1
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
fADC12CLK = 5 MHz,
3 V
0.5
0.7
mA
ADC12ON = 0, REFON = 1, REF2_5V = 1
Operating supply current
IREF+
into AVCC terminal
(4)
2.2 V
0.5
0.7
fADC12CLK = 5 MHz,
mA
ADC12ON = 0, REFON = 1, REF2_5V = 0
3 V
0.5
0.7
Only one terminal can be selected at one time,
CI
Input capacitance(5)
2.2 V
40
pF
P6.x/Ax
Input MUX ON
RI
0 V
≤ VAx ≤ VAVCC
3 V
2000
resistance(5)
(1)
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
(2)
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(3)
The internal reference supply current is not included in current consumption parameter IADC12.
(4)
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables settling of the built-in reference before starting an A/D conversion.
(5)
Not production tested, limits verified by design.
12-Bit ADC, External Reference
(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
VeREF+
Positive external reference voltage input
VeREF+ > VREF–/VeREF–
(2)
1.4
VAVCC
V
VREF–/VeREF–
Negative external reference voltage input
VeREF+ > VREF–/VeREF–
(3)
0
1.2
V
(VeREF+ –
Differential external reference voltage input
VeREF+ > VREF–/VeREF–
(4)
1.4
VAVCC
V
VREF–/VeREF–)
IVeREF+
Static leakage current
0 V
≤ VeREF+ ≤ VAVCC
2.2 V/3 V
±1
A
IVREF–/VeREF–
Static leakage current
0 V
≤ VeREF– ≤ VAVCC
2.2 V/3 V
±1
A
(1)
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2)
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3)
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4)
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Copyright
2007–2011, Texas Instruments Incorporated
61
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