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参数资料
型号： MSP430F2416TZQWR
厂商： TEXAS INSTRUMENTS INC
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PBGA113
封装： GREEN, PLASTIC, BGA-113
文件页数： 68/102页
文件大小： 1509K
代理商： MSP430F2416TZQWR
RO/P(DAC12_x)
Max
0.3
AVCC
AVCC0.3V
VOUT
Min
RLoad
AVCC
CLoad= 100pF
2
ILoad
DAC12
O/P(DAC12_x)
MSP430F261x
MSP430F241x
SLAS541H
– JUNE 2007 – REVISED MAY 2011
www.ti.com
12-Bit DAC Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
0
0.005
DAC12AMPx = 7
No Load, VeREF+ = AVCC,
AVCC -
DAC12_xDAT = 0FFFh, DAC12IR = 1,
AVCC
0.05
DAC12AMPx = 7
Output voltage range(1)
VO
2.2 V/3 V
V
(see Figure 44)
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
0
0.1
DAC12AMPx = 7
RLoad = 3 kΩ, VeREF+ = AVCC,
AVCC -
DAC12_xDAT = 0FFFh, DAC12IR = 1,
AVCC
0.13
DAC12AMPx = 7
Maximum DAC12 load
CL(DAC12)
2.2 V/3 V
100
pF
capacitance
2.2 V
-0.5
0.5
Maximum DAC12 load
IL(DAC12)
mA
current
3 V
-1
1
RLoad = 3 kΩ, VO/P(DAC12) = 0 V,
150
250
DAC12AMPx = 7, DAC12_xDAT = 0h
RLoad = 3 kΩ, VO/P(DAC12) = AVCC,
Output resistance (see
DAC12AMPx = 7,
150
250
RO/P(DAC12)
2.2 V/3 V
Ω
Figure 44)
DAC12_xDAT = 0FFFh
RLoad = 3 kΩ,
0.3 V
< VO/P(DAC12) < AVCC - 0.3 V,
1
4
DAC12AMPx = 7
(1)
Data is valid after the offset calibration of the output amplifier.
Figure 44. DAC12_x Output Resistance Tests
12-Bit DAC Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
DAC12IR = 0(1)(2)
AVCC / 3
AVCC + 0.2
Reference input
VeREF+
2.2 V/3 V
V
voltage range
DAC12IR = 1(3)(4)
AVCC
AVCC + 0.2
DAC12_0 IR = DAC12_1 IR = 0
20
M
Ω
DAC12_0 IR = 1, DAC12_1 IR = 0
Ri(VREF+),
Reference input
40
48
56
2.2 V/3 V
DAC12_0 IR = 0, DAC12_1 IR = 1
Ri(VeREF+)
resistance
k
Ω
DAC12_0 IR = DAC12_1 IR = 1,
20
24
28
DAC12_0 SREFx = DAC12_1 SREFx(5)
(1)
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2)
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC - VE(O)] / [3 × (1 + EG)].
(3)
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4)
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC - VE(O)] / (1 + EG).
(5)
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
68
Copyright
2007–2011, Texas Instruments Incorporated
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