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参数资料
型号： MSP430F2617TZQWR
厂商： TEXAS INSTRUMENTS INC
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PBGA113
封装： GREEN, PLASTIC, BGA-113
文件页数： 10/102页
文件大小： 1509K
代理商： MSP430F2617TZQWR
MSP430F261x
MSP430F241x
www.ti.com
SLAS541H
– JUNE 2007 – REVISED MAY 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the
CPU enters LPM4 immediately after power-up.
Table 5. Interrupt Sources
SYSTEM
INTERRUPT SOURCE
INTERRUPT FLAG
WORD ADDRESS
PRIORITY
INTERRUPT
Power-up
PORIFG
External reset
RSTIFG
Watchdog Timer+
WDTIFG
Reset
0FFFEh
31, highest
Flash key violation
KEYV
PC out-of-range(1)
See (2)
NMI
NMIIFG
(Non)maskable,
Oscillator fault
OFIFG
(Non)maskable,
0FFFCh
30
Flash memory access violation
ACCVIFG(2)(3)
(Non)maskable
Timer_B7
TBCCR0 CCIFG(4)
Maskable
0FFFAh
29
TBCCR1 to TBCCR6 CCIFGs,
Timer_B7
Maskable
0FFF8h
28
TBIFG(2)(4)
Comparator_A+
CAIFG
Maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
Maskable
0FFF4h
26
Timer_A3
TACCR0 CCIFG(4)
Maskable
0FFF2h
25
TACCR1 CCIFG
Timer_A3
Maskable
0FFF0h
24
TACCR2 CCIFG(2)(4)
USCI_A0/USCI_B0 receive
UCA0RXIFG, UCB0RXIFG(2)(5)
Maskable
0FFEEh
23
USCI_B0 I2C status
USCI_A0/USCI_B0 transmit
UCA0TXIFG, UCB0TXIFG(2)(6)
Maskable
0FFECh
22
USCI_B0 I2C receive/transmit
ADC12
ADC12IFG(2)(4)
Maskable
0FFEAh
21
0FFE8h
20
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7(2)(4)
Maskable
0FFE6h
19
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7(2)(4)
Maskable
0FFE4h
18
USCI_A0/USCI_B1 receive
UCA1RXIFG, UCB1RXIFG(2)(5)
Maskable
0FFE2h
17
USCI_B1 I2C status
USCI_A1/USCI_B1 transmit
UCA1TXIFG, UCB1TXIFG(2)(6)
Maskable
0FFE0h
16
USCI_B1 I2C receive/transmit
DMA0IFG, DMA1IFG,
DMA
Maskable
0FFDEh
15
DMA2IFG(2)(4)
DAC12
DAC12_0IFG, DAC12_1IFG(2)(4)
Maskable
0FFDCh
14
See (7)(8)
0FFDAh to 0FFC0h
15 to 0, lowest
(1)
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2)
Multiple source flags
(3)
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4)
Interrupt flags are located in the module.
(5)
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
(6)
In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
(7)
The address 0FFBEh is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
(8)
The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
Copyright
2007–2011, Texas Instruments Incorporated
15
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