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| 型号： | MSP430F5152IRSB |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, RISC MICROCONTROLLER, PQCC40 |
| 封装： | PLASTIC, WQFN-40 |
| 文件页数： | 6/61页 |
| 文件大小： | 915K |
| 代理商： | MSP430F5152IRSB |
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PRODUCTPREVIEW
MSP430F51x1
MSP430F51x2
SLAS619 – AUGUST 2010
www.ti.com
Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to Port P1, Port
P2, and Port P3.
Table 8. Port Mapping, Mnemonics and Functions
Value
PxMAPy Mnemonic
Input Pin Function
Output Pin Function
0
PM_NONE
None
DVSS
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
1
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (Direction controlled by USCI - output)
2
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
3
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCA0RXD
USCI_A0 UART RXD (Direction controlled by USCI - input)
4
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
5
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
6
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI)
7
PM_TD0.0
TD0 input capture channel 0
TD0 output compare channel 0
8
PM_TD0.1
TD0 input capture channel 1
TD0 output compare channel 1
9
PM_TD0.2
TD0 input capture channel 2
TD0 output compare channel 2
10
PM_TD1.0
TD1 input capture channel 0
TD1 output compare channel 0
11
PM_TD1.1
TD1 input capture channel 1
TD1 output compare channel 1
12
PM_TD1.2
TD1 input capture channel 2
TD1 output compare channel 2
PM_CLR1TD0.0
TD0 external clear input
13
TD0 output compare channel 0
PM_FLT1_2TD0.0
TD0 fault input channel 2
14
PM_FLT1_0TD0.1
TD0 fault input channel 0
TD0 output compare channel 1
15
PM_FLT1_1TD0.2
TD0 fault input channel 1
TD0 output compare channel 2
TD1 external clear input (controlled
PM_CLR2TD1.0
by module input enable)
16
TD1 output compare channel 0
TD1 fault input channel 1
PM_FLT2_1TD1.0
(controlled by module input enable)
17
PM_FLT2_2TD1.1
TD1 fault input channel 2
TD1 output compare channel 1
18
PM_FLT2_0TD1.2
TD1 fault input channel 0
TD1 output compare channel 2
19
PM_TD0.0SMCLK
TD0 input capture channel 0
SMCLK output
20
PM_TA0CLKCBOUT
TA0 input clock
Comparator_B output
21
PM_TD0CLKMCLK
TD0 input clock
MCLK output
22
PM_TA3_0
TA0 input capture channel 0
TA0 output compare channel 0
23
PM_TA3_1
TA0 input capture channel 1
TA0 output compare channel 1
24
PM_TA3_2
TA0 input capture channel 2
TA0 output compare channel 2
25
PM_DMAE0SMCLK
DMAE0 input
SMCLK output
26
PM_DMAE1MCLK
DMAE1 input
MCLK output
27
PM_DMAE2SVM
DMAE2 input
SVM output
28
PM_TD0OUTH
TD0 tristate input
ADC10CLK
29
PM_TD1OUTH
TD1 tristate input
ACLK
30
Reserved
None
DVSS
Disables the output driver as well as the input Schmitt-trigger to prevent
31 (0FFh)(1)
PM_ANALOG
parasitic cross currents when applying analog signals.
(1)
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.
14
Copyright 2010, Texas Instruments Incorporated
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