参数资料
型号: MSP430F5502IRGZ
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQCC48
封装: PLASTIC, VQFN-48
文件页数: 15/99页
文件大小: 1134K
代理商: MSP430F5502IRGZ
PRODUCTPREVIEW
MSP430F550x
SLAS645B – JULY 2009 – REVISED JULY 2010
www.ti.com
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.
Each sector 0 to n can be complete disabled, however data retention is lost.
Each sector 0 to n automatically enters low power retention mode when possible.
For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx Family User's Guide, literature number
Digital I/O
There are up to six 8-bit I/O ports implemented: For 64 pin options, P1, P2, P4, P6, and are complete, P5 is
reduced to 6-bit I/O and P3 to 5-bit I/O. For 48 pin options, P6 is reduced to 4-bit I/O, P2 to 1-bit I/O and P3 is
completely removed. Port PJ contains four individual I/O ports, common to all devices.
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Drive strength on all ports is programmable.
Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P6) or word-wise in pairs (PA through PC).
Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4.
Table 9. Port Mapping, Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
PM_CBOUT0
-
Comparator_B output
1
PM_TB0CLK
TB0 clock input
PM_ADC10CLK
-
ADC10CLK
2
PM_DMAE0
DMAE0 input
PM_SVMOUT
-
SVM output
3
TB0 high impedance input
PM_TB0OUTH
TB0OUTH
4
PM_TB0CCR0A
TB0 CCR0 capture input CCI0A
TB0 CCR0 compare output Out0
5
PM_TB0CCR1A
TB0 CCR1 capture input CCI1A
TB0 CCR1 compare output Out1
6
PM_TB0CCR2A
TB0 CCR2 capture input CCI2A
TB0 CCR2 compare output Out2
7
PM_TB0CCR3A
TB0 CCR3 capture input CCI3A
TB0 CCR3 compare output Out3
8
PM_TB0CCR4A
TB0 CCR4 capture input CCI4A
TB0 CCR4 compare output Out4
9
PM_TB0CCR5A
TB0 CCR5 capture input CCI5A
TB0 CCR5 compare output Out5
10
PM_TB0CCR6A
TB0 CCR6 capture input CCI6A
TB0 CCR6 compare output Out6
PM_UCA1RXD
USCI_A1 UART RXD (Direction controlled by USCI - input)
11
PM_UCA1SOMI
USCI_A1 SPI slave out master in (direction controlled by USCI)
PM_UCA1TXD
USCI_A1 UART TXD (Direction controlled by USCI - output)
12
PM_UCA1SIMO
USCI_A1 SPI slave in master out (direction controlled by USCI)
22
Copyright 2009–2010, Texas Instruments Incorporated
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