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参数资料
型号： MSP430F6638IPZR
厂商： TEXAS INSTRUMENTS INC
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP100
封装： PLASTIC, QFP-100
文件页数： 56/105页
文件大小： 1077K
代理商： MSP430F6638IPZR
PRODUCTPREVIEW
MSP430F663x
SLAS566A – JUNE 2010 – REVISED JULY 2010
www.ti.com
Wake-up from Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
PMMCOREV = 0, SVSMLRRL = 0,
5
SVSLFP = 1
PMMCOREV = 1, SVSMLRRL = 1,
5
SVSLFP = 1
tFAST-WAKE-
Wake-up time from LPM2, LPM3, or
2.2 V/3 V
s
UP
LPM4 to active mode(1)
PMMCOREV = 2, SVSMLRRL = 2,
5
SVSLFP = 1
PMMCOREV = 3, SVSMLRRL = 3,
5
SVSLFP = 1
PMMCOREV = 0, SVSMLRRL = 0,
150
SVSLFP = 0
PMMCOREV = 1, SVSMLRRL = 1,
150
SVSLFP = 0
tSLOW-WAKE-
Wake-up time from LPM2, LPM3 or
2.2 V/3 V
s
UP
LPM4 to active mode(2)
PMMCOREV = 2, SVSMLRRL = 2,
150
SVSLFP = 0
PMMCOREV = 3, SVSMLRRL = 3,
150
SVSLFP = 0
tWAKE-UP
Wake-up time from LPM5 to active
2.2 V/3 V
2
3
ms
LPM5
mode(3)
tWAKE-UP-
Wake-up time from RST or BOR
2
3
ms
RESET
event to active mode(3)
(1)
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the
MSP430x5xx Family User's Guide (SLAU208).
(2)
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide
(SLAU208).
(3)
This value represents the time from the wakeup event to the reset vector execution.
Timer_A, Timers TA0, TA1, and TA2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
fTA
Timer_A input clock frequency
External: TACLK
1.8 V/ 3 V
20
MHz
Duty cycle = 50% ± 10%
All capture inputs.
tTA,cap
Timer_A capture timing
Minimum pulse width required for
1.8 V/ 3 V
20
ns
capture.
Timer_B, Timer TB0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Internal: SMCLK, ACLK
fTB
Timer_B input clock frequency
External: TBCLK
1.8 V/ 3 V
20
MHz
Duty cycle = 50% ± 10%
All capture inputs.
tTB,cap
Timer_B capture timing
Minimum pulse width required for
1.8 V/ 3 V
20
ns
capture.
54
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Copyright 2010, Texas Instruments Incorporated
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