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参数资料
型号： MSP430FG4617IPZ
厂商： TEXAS INSTRUMENTS INC
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQFP100
封装： GREEN, PLASTIC, LQFP-100
文件页数： 61/110页
文件大小： 1605K
代理商： MSP430FG4617IPZ
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I APRIL 2006 REVISED MARCH 2011
54
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 26)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Resolution
(12-bit Monotonic)
12
bits
INL
Integral nonlinearity
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
±20
±80
LSB
INL
Integral nonlinearity
(see Note 1)
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
±2.0
±8.0
LSB
DNL
Differential nonlinearity
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
±04
±10
LSB
DNL
Differential nonlinearity
(see Note 1)
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
±0.4
±1.0
LSB
Offset voltage without
calibration
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
±21
EO
calibration
(see Notes 1, 2)
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
±21
mV
Offset voltage with
calibration
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
±25
mV
calibration
(see Notes 1, 2)
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3 V
±2.5
dE(O)/dT
Offset error
temperature coefficient
(see Note 1)
2.2 V/3 V
±30
μV/°C
E
Gain error (see Note 1)
VREF = 1.5 V
2.2 V
±350 % FSR
EG
Gain error (see Note 1)
VREF = 2.5 V
3 V
±3.50 % FSR
dE(G)/dT
Gain temperature
coefficient (see Note 1)
2.2 V/3 V
10
ppm of
FSR/
°C
Time for offset calibration
DAC12AMPx = 2
100
tOffset_Cal
Time for offset calibration
(see Note 3)
DAC12AMPx = 3,5
2.2 V/3 V
32
ms
tOffset_Cal
(see Note 3)
DAC12AMPx = 4,6,7
2.2 V/3 V
6
ms
NOTES:
1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VeREF+/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx = {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during
calibration may effect accuracy and is not recommended.
Positive
Negative
VR+
Gain Error
Offset Error
DAC Code
DAC VOUT
Ideal transfer
function
RLoad =
AVCC
CLoad = 100pF
2
DAC Output
Figure 26. Linearity Test Load Conditions and Gain/Offset Definition
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