参数资料
型号: MSP430G2332IPW20
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, RISC MICROCONTROLLER, PDSO20
封装: GREEN, PLASTIC, TSSOP-20
文件页数: 21/55页
文件大小: 868K
代理商: MSP430G2332IPW20
MSP430G2x32
MSP430G2x02
SLAS723D
– DECEMBER 2010 – REVISED AUGUST 2011
Crystal Oscillator, XT1, Low-Frequency Mode
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
LFXT1 oscillator crystal
fLFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
32768
Hz
frequency, LF mode 0, 1
LFXT1 oscillator logic level
fLFXT1,LF,logic
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
1.8 V to 3.6 V
10000
32768
50000
Hz
LF mode
XTS = 0, LFXT1Sx = 0,
500
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
OALF
k
LF crystals
XTS = 0, LFXT1Sx = 0,
200
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
Integrated effective load
CL,eff
pF
capacitance, LF mode(2)
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
XTS = 0, Measured at P2.0/ACLK,
Duty cycle
LF mode
2.2 V
30
50
70
%
fLFXT1,LF = 32768 Hz
Oscillator fault frequency,
fFault,LF
XTS = 0, XCAPx = 0, LFXT1Sx = 3(4)
2.2 V
10
10000
Hz
LF mode(3)
(1)
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2)
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(3)
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4)
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TA
VCC
MIN
TYP
MAX
UNIT
fVLO
VLO frequency
-40
°C to 85°C
3 V
4
12
20
kHz
dfVLO/dT
VLO frequency temperature drift
-40
°C to 85°C
3 V
0.5
%/
°C
dfVLO/dVCC
VLO frequency supply voltage drift
25
°C
1.8 V to 3.6 V
4
%/V
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
SMCLK
fTA
Timer_A input clock frequency
fSYSTEM
MHz
Duty cycle = 50%
± 10%
tTA,cap
Timer_A capture timing
TA0, TA1
3 V
20
ns
28
Copyright
2010–2011, Texas Instruments Incorporated
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