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| 型号： | MT18HVF6472PY-53EXX |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封装： | LEAD FREE, DIMM-240 |
| 文件页数： | 8/47页 |
| 文件大小： | 1012K |
| 代理商： | MT18HVF6472PY-53EXX |
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PDF: 09005aef81c753e1/ Source: 09005aef81c753af
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HVF18C64_128_256x72G_2.fm - Rev. A 8/05 EN
16
2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x72, SR) 240-Pin DDR2 VLP RDIMM
Mode Register (MR)
Power-Down Mode
Active power-down (PD) mode is defined by bit M12 as shown in Figure 5, "Mode Regis-
ter (MR) Definition," on page 14. PD mode allows the user to determine the active
power-down mode, which determines performance vs. power savings. PD mode bit M12
does not apply to precharge power-down mode.
When bit M12 = 0, standard Active Power-down mode or ‘fast-exit’ active power-down
mode is enabled. The tXARD parameter is used for ‘fast-exit’ active power-down exit
timing. The DLL is expected to be enabled and running during this mode.
When bit M12 = 1, a lower power active power-down mode or ‘slow-exit’ active power-
down mode is enabled. The tXARDS parameter is used for ‘slow-exit’ active power-down
exit timing. The DLL can be enabled, but ‘frozen’ during active power-down mode since
the exit-to-READ command timing is relaxed. The power difference expected between
PD ‘normal’ and PD ‘low-power’ mode is defined in the IDD table.
CAS Latency (CL)
The CAS Latency (CL) is defined by bits M4–M6 as shown in Figure 5, "Mode Register
(MR) Definition," on page 14. CAS Latency is the delay, in clock cycles, between the reg-
istration of a READ command and the availability of the first bit of output data. The CAS
Latency can be set to 3, 4, or 5 clocks. CAS Latency of 6 clocks is a JEDEC optional feature
and may be enabled in future speed grades. DDR2 SDRAM devices do not support any
half clock latencies. Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
DDR2 SDRAM devices also support a feature called Posted CAS additive latency (AL).
This feature allows the READ command to be issued prior to tRCD(MIN) by delaying the
internal command to the DDR2 SDRAM device by AL clocks. The AL feature is described
in more detail in the Extended Mode Register (EMR) and Operational sections.
Examples of CL = 3 and CL = 4 are shown in Figure 6, CAS Latency (CL); both assume AL
= 0. If a READ command is registered at clock edge n, and the CAS Latency is m clocks,
the data will be available nominally coincident with clock edge n + m (this assumes AL =
0).
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相关代理商/技术参数 |
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| MT18HVF6472Y-53EB1 | 功能描述:MODULE DDR2 512MB 240-DIMM VLP RoHS:是 类别:存储卡，模块 >> 存储器 - 模块 系列:- 标准包装:100 系列:- 存储器类型:SDRAM 存储容量:1GB 速度:133MHz 特点:- 封装/外壳:168-DIMM |
| MT18HVS25672CHY-53EE1 | 制造商:Micron Technology Inc 功能描述:2GB 256MX72 DDR2 SDRAM MODULE PBF VLPSOCDIMM 1.8V NON BUF - Trays |
| MT18HVS25672CHY-667E1 | 制造商:Micron Technology Inc 功能描述:2GB 256MX72 DDR2 SDRAM MODULE PBF VLPSOCDIMM 1.8V NON BUF - Trays |
| MT18HVS25672PKY-667E1 | 制造商:Micron Technology Inc 功能描述: |
| MT18HVS25672PKY-667G1 | 制造商:Micron Technology Inc 功能描述: |
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