1
16 Meg x 4 FPM DRAM
D21_2.p65 – Rev. 5/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
16 MEG x 4
FPM DRAM
FEATURES
Single +3.3V ±0.3V power supply
Industry-standard x4 pinout, timing, functions,
and packages
13 row, 11 column addresses (A7)
12 row, 12 column addresses (T8)
High-performance CMOS silicon-gate process
All inputs, outputs and clocks are LVTTL-compat-
ible
FAST-PAGE-MODE (FPM) access
4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
Optional self refresh (S) for low-power data
retention
OPTIONS
Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
MARKING
T8
A7
Plastic Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
DJ
TG
Timing
50ns access
60ns access
-5
-6
Refresh Rates
Standard Refresh
Self Refresh (128ms period)
None
S*
NOTE:
1. The 16 Meg x 4 FPM DRAM base number
differentiates the offerings in one place—
MT4LC16M4A7. The fifth field distinguishes
various options: A7 designates an 8K refresh and
T8 designates a 4K refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC16M4A7DJ
DRAM
MT4LC16M4A7, MT4LC16M4T8
www.micronsemi.com/mti/msp/html/datasheet.html67,108,864 bits organized in a x4 configuration. The
each. The 16,777,216 memory locations are arranged in
4,096 rows by 4,096 columns for the MT4LC16M4T8.