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参数资料
| 型号： | MT5C2561C-35IT |
| 厂商： | AUSTIN SEMICONDUCTOR INC |
| 元件分类： | SRAM |
| 英文描述： | 256K X 1 STANDARD SRAM, 35 ns, CDIP24 |
| 封装： | 0.300 INCH, CERAMIC, DIP-24 |
| 文件页数： | 6/11页 |
| 文件大小： | 81K |
| 代理商： | MT5C2561C-35IT |
SRAM
MT5C2561
MT5C2561
Rev. 2.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < T
C < 125
oC; V
CC = 5V +10%)
MIN
MAX
MIN
MAX
UNITS
NOTES
READ CYCLE
READ cycle time
tRC
35
45
ns
Address access time
tAA
35
45
ns
Chip Enable access time
tACE
35
45
ns
Output hold from address change
tOH
33
ns
Chip Enable to output in Low-Z
tLZCE
33
ns
7
Chip disable to output in High-Z
tHZCE
20
ns
6, 7
Chip Enable to power-up time
tPU
00
ns
4
Chip disable to power-down time
tPD
35
45
ns
4
WRITE CYCLE
WRITE cycle time
tWC
35
45
ns
Chip Enable to end of write
tCW
30
40
ns
Address valid to end of write
tAW
30
40
ns
Address setup time
tAS
00
ns
Address hold from end of write
tAH
55
ns
WRITE pulse width
tWP
30
40
ns
Data setup time
tDS
20
ns
Data hold time
tDH
00
ns
Write disable to output in Low-Z
tLZWE
00
ns
7
Write Enable to output in High-Z
tHZWE
0
15
0
20
ns
6, 7
-35
-45
DESCRIPTION
SYMBOL
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