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参数资料
| 型号： | MT5TL4L32T-90IT |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 8/31页 |
| 文件大小： | 584K |
| 代理商： | MT5TL4L32T-90IT |
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MUAC Routing Coprocessor
2002, Micron Technology Inc.
DS-MUAC RCP 8K and 4K.fm - Rev March/13/02/ 02:20 PM
16
ADVANCE
Melody Routing Coprocessor
CONTROL STATE DESCRIPTIONS
REGISTER READ/WRITE
Control State:
No Operation
Mnemonic:
NOP Binary
Binary Op-Code: XXX XXX 000 011
W#: LOW
AV#: HIGH
PA:AA: n/c
Scope: n/a
Description: No operation. The device performs no
operation during the cycle. No existing states change.
DSC must be LOW.
Control State:
Read Next Free Address
Mnemonic:
RD NFA
Binary Op-Code: XXX XXX 000 011
W#: HIGH
AV#: HIGH
PA:AA: n/c
Scope: NFD
Description: Reads the value of the Next Free address
on the DQ11–0/DQ12–0 bus. In a vertically cascaded
system this will be in the device whose FI# = LOW and
FF# = HIGH, and at the highest-priority location whose
Validity bit is set HIGH. This value is the address of the
location where a subsequent Write at Next Free Address
cycle will be written. The Page address of the device
value is output DQ19–16; DQ31–20 are LOW. DSC must
be LOW.
Control State:
Write Address Register
Mnemonic:
WR AR{MRnnn}
Binary Op-Code: XXX nnn 000 100
W#: LOW
AV#: HIGH
PA:AA: n/c
Scope: AS
Description: Writes data from the DQ31–0 bus to the
Address register. The write is masked by the contents of
Mask Register nnn. When nnn = 000 no mask is used;
when masking is selected, only bits in the addressed
location that correspond to LOW values in the selected
mask register are updated. DSC must be LOW.
Control State:
Read Address Register
Mnemonic:
RD AR
Binary Op-Code: XXX XXX 000 100
W#: HIGH
AV#: HIGH
PA:AA: n/c
Scope: S
Description: Reads the contents of the Address
register to the DQ31–0 bus. DSC must be LOW.
Control State:
Write Configuration Register
Mnemonic:
WR FR{MRnnn}
Binary Op-Code: XXX nnn 000 110
W#: LOW
AV#: HIGH
PA:AA: n/c
Scope: AS
Description: Writes data from the DQ31–0 bus to
the Configuration register. The write is masked by the
contents of Mask Register nnn. When nnn = 000 no
mask is used; when masking is selected, only bits in
the addressed location that correspond to LOW values
in the selected mask register are updated. DSC must be
LOW.
Control State:
Read Configuration Register
Mnemonic:
RD FR
Binary Op-Code: XXX XXX 000 110
W#: HIGH
AV#: HIGH
PA:AA: n/c
Scope: S
Description: Reads the contents of the Configuration
register to the DQ31–0 bus. DSC must be LOW.
Control State:
Write Device Select Register
Mnemonic:
WR DS{MRnnn}
Binary Op-Code: XXX nnn 001 000
W#: LOW
AV#: HIGH
PA:AA: n/c
Scope: AS
Description: Writes data from the DQ31–0 bus to the
Device Select register. The write is masked by the
contents of Mask Register nnn. When nnn = 000 no
mask is used; when masking is selected, only bits in the
addressed location that correspond to LOW values in
the selected mask register are updated. DSC must be
LOW.
Control State:
Read Device Select Register
Mnemonic:
RD DS
Binary Op-Code: XXX XXX 001 000
W#: HIGH
AV: HIGH
PA:AA: n/c
Scope: S
Description: Reads the contents of the Device Select
register to the DQ31–0 bus. DSC must be LOW.
Control State:
Read Status Register
Mnemonic:
RD SR
Binary Op-Code: XXX XXX 000 111
W#: HIGH
AV#: HIGH
PA:AA: n/c
Scope: HPD/S
Description: Reads the contents of the Status register
to the DQ31–0 bus. After a Comparison or Read/Write at
Highest-Priority Matching Address cycle only the
highest-priority device with a match responds to this
control state; in the event of a mismatch, the lowest-
priority device responds. After a random access Read or
Write cycle into the Memory array, RD SR will take place
in any selected device. DSC must be LOW.
Control State:
Write Comparand Register
Mnemonic:
WRs CR{MRnnn}
Binary Op-Code: XXX nnn 000 101
W#: LOW
AV#: HIGH
PA:AA: n/c
Scope: AS
Description: Writes data from the DQ31–0 bus to
bits 31-0 (DSC LOW) or 63-32 (DSC HIGH) of the
Comparand register. The write is masked by bits 31–0
(DSC LOW) or 63-32 (DSC HIGH) of Mask Register
nnn. When nnn = 000 no mask is used; when masking
is selected, only bits in the addressed location that
correspond to LOW values in the selected mask
register are updated.
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