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参数资料
| 型号： | MT8952BP1 |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封装： | LEAD FREE, PLASTIC, MS-018AB, LCC-28 |
| 文件页数： | 27/32页 |
| 文件大小： | 602K |
| 代理商： | MT8952BP1 |
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MT8952B
Data Sheet
4
Zarlink Semiconductor Inc.
Table 1 - Register Addresses
Introduction
The MT8952B HDLC Protocol Controller handles bit oriented protocol structure and formats the data as per the
packet switching protocol defined in the X.25 (Level 2) recommendations of the CCITT. It transmits and receives the
packeted data (information or control) serially in a format shown in Figure 3, while providing the data transparency
by zero insertion and deletion. It generates and detects the flags, various link channel states and the abort
sequence. Further, it provides a cyclic redundancy check on the data packets using the CCITT defined polynomial.
In addition, it can generate and detect a Go Ahead sequence and recognize a single byte address in the received
frame. There is also a provision to disable the protocol functions and provide transparent access to the serial bus
through the parallel port.
Frame Format
All frames start with an opening flag and end with a closing flag as shown in Figure 3. Between these two flags, a
frame contains the data and the frame check sequence (FCS).
Figure 3 - Frame Format
Flag
The flag is a unique pattern of 8 bits (01111110) defining the frame boundary. The transmit section generates the
flags and appends them automatically to the frame to be transmitted. The receive section searches the incoming
packets for flags on a bit-by-bit basis and establishes frame synchronization. The flags are used only to identify and
synchronize the received frame and are not transferred to the FIFO.
Data
The data field refers to the Address, Control and Information fields defined in the CCITT recommendations. A valid
frame should have a data field of at least 16 bits. The first byte in the data field is the address of the frame. If RxAD
Address Bits
Registers
A3
A2
A1
A0
Read
Write
0000
FIFO Status
-
0001
Receive Data
Transmit Data
0010
Control
0011
Receive Address
0100
C-Channel Control (Transmit)
0101
Timing Control
0110
Interrupt Flag
Watchdog Timer
0111
Interrupt Enable
1000
General Status
-
1001
C-Channel Status (Receive)
-
FLAG
DATA FIELD
FCS
FLAG
One
Byte
n Bytes
(n
≥ 2)
Two
Bytes
One
Byte
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT8952BPR | 制造商:Microsemi Corporation 功能描述: |
| MT8952BPR1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel |
| MT8952BS | 制造商:Microsemi Corporation 功能描述: |
| MT8952BS1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC PROTOCOL CONTROLLER - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC PROTOCOL CONTROLLER |
| MT8960 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Integrated PCM Filter Codec |
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