
HIGH AVAILABLE GAIN WHEN BIASED FOR LOW-NOISE
EXCELLENT FOR BROADBAND GAIN OR OSCILLATOR BUFFER
APPLICATIONS
0.3 MICRON REFRACTORY METAL/GOLD GATE
250 MICRON GATE WIDTH
CHOICE OF CHIP AND TWO PACKAGE TYPES
SYMBOL
PARAMETERS AND CONDITIONS
FREQ
UNITS
MIN
TYP
P1dB
SSG
NFopt
GA
Output Power at 1 dB Compression
VDS= 4.5 V Idss= 0.6 IDS=30mA
Small Signal Gain
VDS= 4.5 V Idss= 0.6 IDS=30mA
Optimum Noise Figure
VDS= 3.0V IDS= 10mA
Gain at Optimum Noise Figure
VDS= 3.0V IDS= 10mA
12 GHz
dBm
dB
10.0
16.0
11.0
1.5
8.0
RF SPECIFICATIONS AT Ta = 25
°°°°°C
MwT-S7
18 GHz High Gain, Low Noise
GaAs FET
12 GHz
DESCRIPTION
The MwT-S7 is a GaAs MESFET device whose nominal quarter-micron gate length and 250 micron gate width make it ideally suited to
applications requiring high-gain in the 500 MHz to 18 GHz frequency range while exhibiting a low noise figure. The straight geometry of
the MwT-S7 makes it equally effective for either wideband (e.g. 6 to 18 GHz) or narrow-band applications. Procesing which guarantees
low phase noise makes the MwT-S7 particularly attractive for oscillator applications. The chip is produced using MwT’s reliable metal
system and devices from each wafer are screened to insure reliability. All chips are passivated using MwT’s patented “Diamond-Like
Carbon” process for increased durability, Designers can use MwT’s unique BIN selection feature to choose devices from narrow Idss
ranges, insuring consistent circuit operation.
50
356
100
50
241
CHIP THICKNESS = 125
DC SPECIFICATIONS AT Ta = 25
°°°°°C
SYMBOL
PARAM. & CONDITIONS
UNITS
MIN
TYP
MAX
IDSS
Gm
Vp
BVGSO
BVGDO
Saturated Drain Current
Vds= 4.0 V VGS= 0.0 V
Transconductance
Vds= 2.0 V VGS= 0.0 V
Pinch-off Voltage
Vds= 3.0 V IDS= 5.0 mA
Gate-to-Source Breakdown Volt.
Igs= -1.0 mA
Gate-to-Drain Breakdown Volt.
Igd= -1.0 mA
mA
26
-1.5
98
mS
45
60
-4.5
V
°°°°°C/W
-4.0
-5.0
-7.0
180
380*
Lg
Rg
Rd
Ld
Cgd
GATE
DRAIN
Cgs
Cpg
Rds
Cds
Cpd
Ri
Rs
Ls
gm
tau
SOURCE
DEVICE EQUIVALENT CIRCUIT MODEL
Gate Bond Wire Inductance
Gate Pad Capacitance
Gate Resistance
Gate-Source Capacitance
Channel Resistance
Gate-Drain Capacitance
Transconductance
Transit Time
Lg
Cpg
Rg
Cgs
Ri
Cgd
gm
tau
0.13
nH
0.05
pF
0.2
0.314
pF
6.9
0.027
pF
69.0
mS
2.0
psec
Source Resistance
Source Inductance
Drain-Source Resistance
Drain-Source Capacitance
Drain Resistance
Drain Pad Capacitance
Drain Inductance
VALUE
PARAMETER
Rs
Ls
Rds
Cds
Rd
Cpd
Ld
2.6
0.025
nH
173
0.07
pF
3.67
0.027
pF
0.159
nH
Rth
Thermal
Resistance
7.0
MwT-S7
18 GHz High Gain, Low Noise
GaAs FET
4268 Solar Way
Fremont
California 94538 Phone: (510) 651-6700 Fax: (510) 651-2208
4268 Solar Way
Fremont
California 94538 Phone: (510) 651-6700 Fax: (510) 651-2208
All rights reserved. MicroWave Technology, Inc. All specifications subject to change without notice.
DC SPECIFICATIONS AT Ta = 25
°°°°°C
RF SPECIFICATIONS AT Ta = 25
°°°°°C
FEATURES
NOTE:
For Package information, please see supplimentary application note from our website at
www.mwtinc.com. When placing order or inquiring, please specify BIN range, wafer no., if
known, and screening level required.
ORDERING INFORMATION
Chip
MwT-S7
Package 71
MwT-S771
Package 73
MwT-S773
All Dimensions in Microns
MwT-S7 Chip,
MwT-S770, S773
*Overall Rth depends on case mounting.
DOWNLOAD ADDITIONAL DATA WWW.MWTINC.COM
IDSS
Recommended IDSS Range
for Optimum P1dB
mA
34-
70
50
70