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参数资料
| 型号： | MX7847KR+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT DL MULT 24SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 设置时间： | 4µs |
| 位数： | 12 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 941mW |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电压，单极；2 电压，双极 |
| 采样率（每秒）： | * |
MX7837/MX7847
_______________Detailed Description
D/A Section
Figure 1 shows a simplified circuit diagram for one of
the DACs and the output amplifier. Using a segmented
scheme, the two MSBs of the 12-bit data word are
decoded to drive the three switches (A to C). The
remaining 10 bits drive the switches (S0 to S9) in a
standard R-2R ladder.
Each switch (A to C) directs 1/4 of the total reference
current, and the remaining current passes through the
R-2R section.
The output amplifier and feedback resistor convert cur-
rent to voltage as follows: VOUT_ = (-D)(VREF_), where D
is the fractional representation of the digital word. (D
can be set from 0 to 4095/4096.)
The output amplifier is capable of developing ±10V
across a 2k
load. It is internally compensated and
settles to 0.01% FSR (1/2LSB) in less than 4s. VOUT
on the MX7837 is not internally connected to RFB.
Interface Logic Information
(MX7847)
Figure 2 shows the MX7847 input control logic. The
device contains two independent DACs, each with its
own
CS input and a common WR input. CSA and WR
control data loading to the DAC A latch, and
CSB and
WR control data loading to the DAC B latch. The latch-
es are edge triggered so that input data is latched to
the respective latch on
WR's rising edge. The same
data will be latched to both DACs if
CSA and CSB are
low and
WR is taken high. Table 1 shows the device
control-logic truth table, and Figure 3 shows the write-
cycle timing diagram.
Table 1. MX7847 Truth Table
X = Don't Care
= Rising Edge Triggered
Interface Logic Information
(MX7837)
The MX7837 input loading structure is configured for
interfacing with 8-bit-wide data-bus microprocessors.
Each DAC has two 12-bit latches: an input latch, and a
DAC latch. Each input latch is subdivided into a least-
significant 8-bit latch and a most-significant 4-bit latch.
The data held in the DAC latches determines the out-
puts. Figure 4 shows the MX7837 input control logic,
and Figure 5 shows the write-cycle timing diagram.
Complete, Dual, 12-Bit
Multiplying DACs
6
_______________________________________________________________________________________
2R
CB
A
S9
S8
S0
VREF
RR
R
R/2
VOUT
AGND
SHOWN FOR ALL 1s ON DAC
DAC A LATCH
DAC B LATCH
CSA
WR
CSB
Figure 1. D/A Simplified Circuit Diagram
t3
t1
t2
t5
t4
VALID DATA
WR
CSA, CSB
DATA
Figure 2. MX7847 Input Control Logic
Figure 3. MX7847 Write-Cycle Timing Diagram
CSA
CSB
WR
Function
X
1
No Data Transfer
1
X
No Data Transfer
0
1
Data Latched to DAC A
1
0
Data Latched to DAC B
0
Data Latched to Both DACs
1
0
Data Latched to DAC A
1
0
Data Latched to DAC B
0
Data Latched to Both DACs
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| MX7847TQ/883B | 制造商:Maxim Integrated Products 功能描述:- Bulk |
| MX7-93PL-C4 | 功能描述:汽车连接器 R/A Pin HEADER 93P RoHS:否 制造商:Amphenol SINE Systems 产品:Contacts 系列:ATP 位置数量: 型式:Female 安装风格: 端接类型: 触点电镀:Nickel |
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