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参数资料
| 型号： | N8xC196MH |
| 厂商： | Intel Corp. |
| 英文描述： | 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER |
| 中文描述： | 8XC196MH工业电机控制CHMOS单片机 |
| 文件页数： | 24/41页 |
| 文件大小： | 292K |
| 代理商： | N8XC196MH |
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
24
The External Memory System Must Meet These Specifications (Continued)
T
LLGX
T
LHDV
T
AVDV
T
RLDV
T
RHDZ
T
RXDX
BUSWIDTH Hold after ALE/ADV# Low
T
OSC
ns
ALE/ADV# High to Input Data Valid
3T
OSC
– 55
3T
OSC
– 55
T
OSC
– 30
T
OSC
ns
Address Valid to Input Data Valid
ns
3
RD# Active to Input Data Valid
ns
3
End of RD# to Input Data Float
ns
Data Hold after RD# Inactive
0
ns
The 8XC196MH will Meet These Specifications
T
XHLH
T
XHLL
T
LHLH
T
LHLL
T
AVLH
T
AVLL
T
LLAX
T
LLRL
T
RLRH
T
RHLH
T
RLAZ
T
LLWL
T
QVWH
T
WLWH
T
WHQX
T
WHLH
T
WHBX
T
WHAX
T
RHBX
T
RHAX
NOTES:
1.
2.
3.
4.
XTAL1 Rising Edge to ALE Rising
20
110
ns
XTAL1 Rising Edge to ALE Falling
20
110
ns
ALE/ADV# Cycle Time
4T
OSC
ns
3
ALE/ADV# High Period
T
OSC
– 10
T
OSC
– 17
T
OSC
– 17
T
OSC
– 40
T
OSC
– 30
T
OSC
– 5
T
OSC
T
OSC
+ 10
ns
Address Valid to ALE/ADV# High
ns
Address Valid to ALE/ADV# Low
ns
Address Hold after ALE/ADV# Low
ns
ALE/ADV# Low to RD# Low
ns
RD# Low Period
T
OSC
+ 25
T
OSC
+ 25
5
ns
3
RD# High to ALE/ADV# High
ns
5
RD# Low to Address Float
ns
ALE/ADV# Low to WR# Low
T
OSC
– 10
T
OSC
– 23
T
OSC
– 30
T
OSC
– 25
T
OSC
– 10
T
OSC
– 10
T
OSC
– 30
T
OSC
– 10
T
OSC
– 30
ns
Data Valid before WR# High
ns
WR# Low Period
ns
3
Data Hold after WR# High
ns
WR# High to ALE/ADV# High
T
OSC
+ 15
ns
5
BHE#, INST Hold after WR# High
ns
A15:8 Hold after WR# High
ns
6
BHE#, INST Hold after RD# High
ns
A15:8 Hold after RD# High
ns
6
Table 11. AC Timing Definitions
(
1
)
(Continued)
Symbol
Parameter
Min
Max
Units
Notes
Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, F
OSC
= 16 MHz.
Exceeding the maximum specification causes additional wait states.
If wait states are used, add 2T
×
n where n= number of wait states.
Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
Assuming back-to-back bus cycles.
8-bit bus only.
5.
6.
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