参数资料
型号: NB100LVEP17MNR2G
厂商: ON Semiconductor
文件页数: 1/10页
文件大小: 0K
描述: IC DRVR ECL QUAD 2.5V/3.3V 24QFN
标准包装: 3,000
系列: 100LVEP
逻辑类型: 差分接收器/驱动器
电源电压: 2.375 V ~ 3.8 V
位数: 4
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN(4x4)
包装: 带卷 (TR)
其它名称: NB100LVEP17MNR2GOS
Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 7
1
Publication Order Number:
NB100LVEP17/D
NB100LVEP17
2.5V / 3.3V Quad Differential
Driver/Receiver
Description
The NB100LVEP17 is a 4-bit differential line receiver. The design
incorporates two stages of gain, internal to the device, making it an
excellent choice for use in high bandwidth amplifier applications.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device.
Features
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
250 ps Typical Propagation Delay
Low Profile QFN Package
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 2.375 V to 3.8 V
Q Output Will Default LOW with Inputs Open or at VEE
VBB Output
PbFree Packages are Available
MARKING
DIAGRAMS*
*For additional marking information, refer to
Application Note AND8002/D.
TSSOP20
DT SUFFIX
CASE 948E
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
N100
VP17
ALYWG
G
1
24
24 PIN QFN
MN SUFFIX
CASE 485L
24
1
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
(Note: Microdot may be in either location)
N100
VP17
ALYWG
G
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