参数资料
| 型号： | NB3N121KMNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 1/11页 |
| 文件大小： | 0K |
| 描述： | IC FANOUT BUFFER 1:21 52QFN |
| 标准包装： | 2,000 |
| 类型： | 扇出缓冲器（分配），数据 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:21 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | HCSL, LVCMOS, LVDS, LVPECL, LVTTL |
| 输出： | HCSL，LVDS |
| 频率 - 最大： | 400MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-VFQFN 裸露焊盘 |
| 供应商设备封装： | 52-QFN（8x8） |
| 包装： | 带卷 (TR) |
Semiconductor Components Industries, LLC, 2012
March, 2012 Rev. 1
1
Publication Order Number:
NB3N121K/D
NB3N121K
3.3V Differential 1:21
Fanout Clock and Data
Driver with HCSL Outputs
Description
The NB3N121K is a differential 1:21 Clock and Data fanout buffer
with Highspeed Current Steering Logic (HCSL) outputs optimized
for ultra low propagation delay variation. The NB3N121K is designed
with HCSL PCI Express clock distribution and FBDIMM applications
in mind.
Inputs can directly accept differential LVPECL, HCSL, and LVDS
LVCMOS, or LVTTL levels are accepted with a proper external Vth
internal 50
W termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475
W resistor from
IREF (Pin 1) to GND per Figure 6. Outputs can also interface to
LVDS receivers when terminated per Figure 11.
The NB3N121K specifically guarantees low output–to–output
skew. Optimal design, layout, and processing minimize skew within a
device and from device to device. System designers can take
advantage of the NB3N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
400 MHz
340 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
100 ps Max Within Device Skew
150 ps Max DevicetoDevice Skew
Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
0.1 ps Typical RMS Additive Phase Jitter
LVDS Output Levels Optional with Interface Termination
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
Typical HCSL Output Level (700 mV PeaktoPeak)
These are PbFree Devices
Applications
Clock Distribution
PCIe I, II, III
Networking
High End Computing
Routers
End Products
Servers
FBDIMM Memory Card
A
= Assembly Site
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
QFN52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
http://onsemi.com
NB3N
121K
AWLYYWWG
1
52
Figure 1. Simplified Logic Diagram
Q0
Q1
Q19
Q20
CLK
VCC
GND
RREF
IREF
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
VTCLK
152
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NB3N15552MNG | 功能描述:时钟缓冲器 VCXO LVPECL 155.52 MHZ RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| NB3N15552MNTXG | 功能描述:时钟缓冲器 VCXO LVPECL 155.52 MHZ RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| NB3N15625MNG | 功能描述:时钟缓冲器 VCXO LVPECL 156.25 MHZ RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| NB3N15625MNTXG | 功能描述:时钟缓冲器 VCXO LVPECL 156.25 MHZ RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| NB3N200SDG | 功能描述:时钟缓冲器 M-LVDS DRIVER RECEIVER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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