参数资料
| 型号： | NB4L16MMNR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 1/12页 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFFER DVR TRANSLA 16-QFN |
| 产品变化通告： | Product Discontinuation 20/Aug/2008 |
| 标准包装： | 3,000 |
| 类型： | 缓冲器/驱动器，变换器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，HSTL，LVCMOS，LVDS，LVPECL，LVTTL |
| 输出： | CML |
| 频率 - 最大： | 3.5GHz |
| 电源电压： | 2.375 V ~ 3.8 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（3x3） |
| 包装： | 带卷 (TR) |
Semiconductor Components Industries, LLC, 2009
August, 2009 Rev. 3
1
Publication Order Number:
NB4L16M/D
NB4L16M
2.5V/3.3V, 5 Gb/s Multi Level
Clock/Data Input to CML
Driver / Receiver / Buffer/
Translator with Internal
Termination
Description
The NB4L16M is a differential driver/receiver/buffer/translator
which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL
and produce 400 mV CML output. The device is capable of receiving,
buffering, and translating a clock or data signal that is as small as
75 mV operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such, it is
ideal for SONET, GigE, Fiber Channel and backplane applications
Differential inputs incorporate internal 50
W termination resistors
and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, HSTL
or LVDS. The differential 16 mA CML output provides matching
internal 50
W termination, and 400 mV output swing when externally
receiver terminated, 50
provide transmission line termination on chip, at the receiver and
driver end, eliminating any use of additional external components.
The VBB, an internally generated voltage supply, is available to this
device only. For singleended input configuration, the unused
complementary differential input is connected to VBB as a switching
reference voltage. The VBB reference output can be used also to
rebias capacitor coupled differential or singleended output signals.
For the capacitor coupled input signals, VBB should be connected to
the VTD pin and bypassed to ground with a 0.01 mF capacitor. When
not used VBB should be left open.
This device is housed in a 3x3 mm 16 pin QFN package.
Application notes, models, and support documentation are available at
Features
Maximum Input Clock Frequency up to 3.5 GHz
Maximum Input Data Rate up to 5.0 Gb/s
< 0.7 ps Maximum Clock RMS Jitter
< 10 ps Maximum Data Dependent Jitter at 2.5 Gb/s
220 ps Typical Propagation Delay
60 ps Typical Rise and Fall Times
CML Output with Operating Range:
VCC = 2.375 V to 3.6 V with VEE = 0 V
CML Output Level (400 mV PeaktoPeak Output),
Differential Output Only
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
PbFree Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
16
NB4L
16M
ALYWG
G
1
Q
Figure 1. Functional Block Diagram
VTD
D
50 W
VTD
50 W
R1
R2
R1
R2
VEE
VCC
(Note: Microdot may be in either location)
1
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| NB4L16MMNR2G | 功能描述:转换 - 电压电平 2.5V/3.3V 5Gb/s Driver/RCVR/Buffer RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| NB4L339 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:3.3V 1:4 Clock Fanout Buffer |
| NB4L339_07 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan−Out Buffer |
| NB4L339MNG | 功能描述:时钟驱动器及分配 2.7V 622MHZ CLK DIST RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| NB4L339MNGEVB | 功能描述:BOARD EVAL FOR NB4L339MNG RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:* 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
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