参数资料
型号: NB4N1158DTG
厂商: ON Semiconductor
文件页数: 5/8页
文件大小: 0K
描述: IC LINK REPLICATOR SER 28-TSSOP
产品变化通告: Product Obsolescence 01/Jul/2009
标准包装: 50
类型: 链路复制器,多路复用器
PLL:
主要目的: 光纤通道,千兆位以太网,HDTV,SATA
输入: LVPECL
输出: LVPECL
电路数: 1
比率 - 输入:输出: 3:3
差分 - 输入:输出: 是/是
电源电压: 3.14 V ~ 3.47 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
NB4N1158
http://onsemi.com
5
Figure 5. NB4N1158 Application Interface Example
NB4N1158
SerDes
TX+
TX-
RX+
RX-
O1+
O1-
I1+
I1-
I+
I-
O+
O-
O+
O-
I+
I-
I1+
I1-
O1+
O1-
RX+
RX-
TX+
TX-
0.01
mF
0.01
mF
0.01
mF
0.01
mF
0.01
mF
0.01
mF
0.01
mF
0.01
mF
0.01
mF
0.01
mF
0.01
mF
0.01
mF
R
RT
R
RT
“R” is 150
W for both 100 W differential or 150 W differential traces.
“RT” matches the differential impedance of the link.
IN+/IN- Input Functionality
The differential inputs are internally biased to
Y1.2 V. In
a
typical
application,
the
differential
inputs
are
capacitor-coupled and will swing symmetrically above and
below 1.2 V, preserving a 50% duty cycle to the outputs.
With this technique, the NB4N1158 will accept any
differential input allowing for LVPECL, CML, LVDS, and
HSTL input levels.
OUT+ / OUT- Outputs
The differential output buffers of the NB4N1158 utilize
standard
Positive
Emitter
Coupled
Logic
(PECL)
architecture for OUT+ and OUT-. The outputs are designed
to drive differential transmission lines with nominally 50
W
or
75
W
characteristic
impedance.
External
DC load/termination with a 50
W resistor to VTT = VDD -
2.0 V is required. See Figure 6 for output termination
scheme.
OEx Output Enable
The NB4N1158 incorporates output enable pins, OE0 and
OE1, that work by powering down the output buffer and
associated driving circuitry. Using this approach results in
both differential outputs going HIGH, and a reduction in IDD
current of approx. 29 mA for each disabled output pair.
When OEx is LOW, outputs are disabled, OUTx+ and
OUTx- are set HIGH.
Power Supply Bypass information
A clean power supply will optimize the performance of
the device. The NB4N1158 provides separate power supply
pins for the digital circuitry (VDD) and LVPECL outputs
(VDDPn). Placing a bypass capacitor of 0.01
mF to 0.1 mF
on each VDD pin will help ensure a noise free VDD power
supply. The purpose of this design technique is to try and
isolate the high switching noise of the digital outputs from
the relatively sensitive digital core logic.
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q
D
Zo = 50 W
50
W
50
W
VTT
VTT = VCC - 2.0 V
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