参数资料
| 型号： | NB6L295MNG |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/13页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 511TAP 24-QFN |
| 标准包装： | 92 |
| 标片/步级数： | 512 |
| 功能： | 多重，可编程 |
| 延迟到第一抽头： | 3.2ns，6.2ns |
| 接头增量： | 11ps |
| 可用的总延迟： | 3.2ns ~ 8.5ns，6.2ns ~ 16.6ns |
| 独立延迟数： | 2 |
| 电源电压： | 2.375 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 管件 |
| 其它名称： | NB6L295MNG-ND NB6L295MNGOS |
NB6L295
http://onsemi.com
6
Table 5. AC CHARACTERISTICS VCC = VCC0 = VCC1 = 2.375 V to 3.6 V, GND = 0 V, TA = 40°C to +85°C (Note 10)
Symbol
Characteristic
Min
Typ
Max
Unit
fSCLK
Serial Clock Input Frequency, 50% Duty Cycle
20
MHz
VOUTPP Output Voltage Amplitude (@ VINPPmin) fin ≤ 1.5 GHz
530
780
mV
fDATA
Maximum Data Rate (Note 14)
2.5
Gb/s
tRange
Programmable Delay Range (@ 50 MHz)
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
Extended Mode
IN0/IN0 to Q1/Q1
0
5.7
11.2
6.9
13.7
ns
tSKEW
Duty Cycle Skew (Note 11)
Within Device Skew Dual Mode
D[8:0] = 0
D[8:0] = 1
0
2
60
5
100
175
ps
Lin
Linearity (Note 12)
$15
$20
ps
ts
Setup Time (@ 20 MHz)
SDIN to SCLK
SLOAD to SCLK
EN to SDIN
0.5
1.5
0.5
0.3
1.0
ns
th
Hold Time
SDIN to SCLK
SLOAD to SCLK
EN to SLOAD
1.0
0.5
0.6
ns
tpwmin
Minimum Pulse Width SLOAD
1
ns
tJITTER
Random Clock Jitter RMS; SETMIN to SETMAX
(Note 13)
fin ≤ 1.5 GHz
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
Extended Mode
IN0/IN0 to Q1/Q1
Deterministic Jitter; SETMIN to SETMAX (Note 14)fDAT
A ≤ 2.5 Gbps
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
3
6
20
10
20
30
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
150
VCC GND
mV
tr, tf
Output Rise/Fall Times (@ 50 MHz), (20% 80%) Qx,
Qx
85
120
170
ps
Symbol
Characteristic
405C
+255C
+855C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
tPLH,
tPHL
Propagation Delay (@ 50 MHz)
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
D[8:0] = 0
D[8:0] = 1
Extended Mode
IIN0/IN0 to Q1/Q1
D[8:0] = 0
D[8:0] = 1
2.7
7.2
5.0
14.2
2.9
8.0
5.5
15.2
3.2
8.8
6.0
17.1
2.8
7.5
5.2
14.8
3.1
8.4
5.8
16.5
3.4
9.3
6.3
18.2
2.9
7.9
5.5
15.6
3.2
9.2
6.2
16.4
3.6
9.9
6.8
19.6
ns
Dt
Step Delay
(Selected D Bit HIGH All Others LOW)
D0 HIGH
D1 HIGH
D2 HIGH
D3 HIGH
D4 HIGH
D5 HIGH
D6 HIGH
D7 HIGH
D8 HIGH
9.6
19.4
40
81
167
338
678
1358
2715
8.7
19
42
85
175
355
714
1432
2861
11
24.4
52
99
196
389
774
1544
3074
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured by forcing VINPPmin and VINPPmax from a 50% duty cycle clock source, VCMR (min and max). All loading with an external
RL = 50 W to VCC. See Figure 20. Input edge rates 40 ps (20% 80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ @ 0.5 GHz.
12.Deviation from a linear delay (actual Min to Max) in the Dual Mode 511 programmable steps.
13.Additive random CLOCK jitter with 50% duty cycle input clock signal.
14.NRZ data at PRBS23 and K28.5.
15.Input and output voltage swing is a singleended measurement operating in differential mode.
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