参数资料
| 型号： | NB7HQ14MMNTXG |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/10页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA BUFFER MUX 1:4 16QFN |
| 标准包装： | 3,000 |
| 系列： | GigaComm™ |
| 类型： | 扇出缓冲器（分配），多路复用器，数据 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，LVDS，LVPECL |
| 输出： | CML |
| 频率 - 最大： | 7GHz |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（3x3） |
| 包装： | 带卷 (TR) |
NB7HQ14M
http://onsemi.com
3
EQEN Q3
Q3 VCCO
GND Q0
Q0
VCC
Q1
Q2
IN
VT
VREFAC
IN
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7HQ14M
Exposed Pad (EP)
Figure 2. QFN16 Pinout (Top View)
Table 1. EQUALIZER ENABLE FUNCTION
EQEN
Function
0
IN / IN Inputs Bypass the Equalizer section
1
Inputs flow through the Equalizer
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IN
LVPECL, CML,
LVDS Input
Noninverted Differential Input. Note 1.
2
VT
Internal 100 W Centertapped Termination Pin for IN / IN
3
VREFAC
Output Voltage Reference for CapacitorCoupled Inputs, only
4
IN
LVPECL, CML,
LVDS Input
Inverted Differential Input. Note 1.
5
EQEN
LVCMOS Input
Equalizer Enable Input; pin will default LOW when left open (has internal pulldown resistor)
6
Q3
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
7
Q3
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
8
VCCO
1.8 V or 2.5 V Positive Supply Voltage for the Qn / Qn CML Outputs
9
Q2
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
10
Q2
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
11
Q1
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
12
Q1
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
13
VCC
2.5 V Positive Supply Voltage for the core
14
Q0
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
15
Q0
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
16
GND
Negative Supply Voltage
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heatsinking
conduit. The pad is electrically connected to the die, and must be electrically and thermally con-
nected to GND on the PC board.
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
is applied on IN / IN input, then, the device will be susceptible to selfoscillation.
2. All VCC, VCCO and GND pins must be externally connected to a power supply for proper operation.
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