参数资料
型号: NB7L1008MMNG
厂商: ON Semiconductor
文件页数: 6/10页
文件大小: 0K
描述: IC CLOCK BUFFER 1:8 8GHZ 32-QFN
特色产品: NB7L1008M 2.5V / 3.3V 1:8 CML Fanout
标准包装: 74
系列: GigaComm™
类型: 扇出缓冲器(分配)
电路数: 1
比率 - 输入:输出: 1:8
差分 - 输入:输出: 是/是
输入: CML,LVCMOS,LVDS,LVPECL,LVTTL
输出: CML
频率 - 最大: 8GHz
电源电压: 2.375 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 管件
产品目录页面: 1115 (CN2011-ZH PDF)
其它名称: NB7L1008MMNGOS
NB7L1008M
http://onsemi.com
5
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0V TA = 40°C to 85°C (Note 10)
Symbol
Characteristic
Min
Typ
Max
Unit
fDATA
Maximum Operating Input Data Rate
10
12
Gb/s
fINCLK
Maximum Input Clock Frequency, VOUTPP w 200 mV
6
8
GHz
VOUTPP
Output Voltage Amplitude (see Figures 2 and 5, Note 11)
fin v 4 GHz
fin v 6 GHz
200
400
350
mV
VCMR
Input Common Mode Range (Differential Configuration,
Note 12, Figure 9)
600
VCC 50
mV
tPLH, tPHL Propagation Delay to Output Differential, IN/IN to Qn/Qn
100
160
250
ps
tPLH TC
Propagation Delay Temperature Coefficient 40°C to +85°C
35
fs/°C
tDC
Output Clock Duty Cycle fin v 6 GHz
45
49/51
55
%
tSKEW
Duty Cycle Skew (Note 13)
Within Device Skew (Note 14)
Device to Device Skew (Note 15)
0.15
7
25
1
25
70
ps
tJITTER
Clock Jitter RMS, 1000 Cycles (Note 16) fin v 6 GHz
Data Dependent Jitter (DDJ) (Note 17) v10 Gb/s
0.2
3
0.8
20
ps
VINPP
Input Voltage Swing (Differential Configuration) (Note 18)
(Figure 5)
100
1200
mV
tr, tf
Output Rise/Fall Times (20% 80%) Qn, Qn
20
45
70
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured using a 400 mV source, 50% duty cycle 1 GHz clock source. All outputs must be loaded with external 50 W to VCC. Input
edge rates 40 ps (20% 80%).
11. Output voltage swing is a singleended measurement operating in differential mode.
12.VIHDMIN ≥ 1100 mV.
13.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ @ 1 GHz.
14.Within device skew compares coincident edges.
15.Device to device skew is measured between outputs under identical transition
16.Additive CLOCK jitter with 50% duty cycle clock signal.
17.Additive PeaktoPeak jitter with input NRZ data at PRBS23.
18.Input voltage swing is a singleended measurement operating in differential mode.
Figure 2. Output Voltage Amplitude (VOUTPP)
vs. Input Frequency (fin) at Ambient
Temperature (Typical)
500
450
400
350
300
250
200
0
1.0
2.0
3.0
8.0
7.0
6.0
5.0
4.0
.
fout, CLOCK OUTPUT FREQUENCY (GHz)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
Q Output Amplitude (mV)
Figure 3. Input Structure
50 W
VT
VCC
IN
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