参数资料
| 型号： | NB7L14MNTXG |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/10页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER 1:4 8GHZ 16-QFN |
| 标准包装： | 3,000 |
| 系列： | GigaComm™ |
| 类型： | 扇出缓冲器（分配） |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，LVCMOS，LVDS，LVPECL，LVTTL |
| 输出： | LVPECL |
| 频率 - 最大： | 8GHz |
| 电源电压： | 2.375 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（3x3） |
| 包装： | 带卷 (TR) |
NB7L14
http://onsemi.com
2
GND Q3
Q3 VCC
GND Q0
Q0
VCC
Q1
Q2
IN
VT
VREFAC
IN
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7L14
Exposed Pad (EP)
Figure 2. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IN
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Noninverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VT
2
VT
Internal 50W Termination Pin for IN/IN inputs.
3
VREFAC
Output Reference Voltage for capacitorcoupled inputs
4
IN
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VT.
5
GND
Negative Supply Voltage
6
Q3
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
7
Q3
LVPECL Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
8
VCC
Positive Supply Voltage
9
Q2
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
10
Q2
LVPECL Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
11
Q1
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
12
Q1
LVPECL Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
13
VCC
Positive Supply Voltage
14
Q0
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
15
Q0
LVPECL Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
16
GND
Negative Supply Voltage
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for im-
proved heat transfer out of package. The exposed pad must be attached to a heatsinking con-
duit. The pad is electrically connected to the die, and must be electrically connected to device
GND.
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN input, then, the device will be susceptible to selfoscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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