参数资料
型号: NB7L585RMNG
厂商: ON Semiconductor
文件页数: 1/9页
文件大小: 0K
描述: IC CLK/DATA BUFFER MUX 1:6 32QFN
标准包装: 74
系列: GigaComm™
类型: 扇出缓冲器(分配),多路复用器,数据
电路数: 1
比率 - 输入:输出: 1:6
差分 - 输入:输出: 是/是
输入: CML,LVDS,LVPECL
输出: RSECL
频率 - 最大: 7GHz
电源电压: 2.375 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 管件
Semiconductor Components Industries, LLC, 2009
October, 2009 Rev. 0
1
Publication Order Number:
NB7L585R/D
NB7L585R
2.5V/3.3V, 7GHz/10Gbps
Differential 2:1 Mux Input to
1:6 RSECL Clock/Data
Fanout Buffer / Translator
MultiLevel Inputs w/ Internal
Termination
Description
The NB7L585R is a differential 1:6 RSECL Clock/Data distribution
chip featuring a 2:1 Clock/Data input multiplexer with an input select
pin. The INx/INx inputs incorporate internal 50
W termination
resistors and will accept LVPECL, CML, or LVDS logic levels.
The NB7L585R produces six identical output copies of Clock or
Data operating up to 7 GHz or 10 Gb/s, respectively. As such,
NB7L585R is ideal for SONET, GigE, Fiber Channel, Backplane and
other Clock/Data distribution applications.
The NB7L585R is powered with either 2.5 V or 3.3 V supply and is
offered in a low profile 5mm x 5mm 32pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7L585R is a member of the GigaComm
family of high
performance clock products.
Features
Maximum Input Data Rate > 10 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 7 GHz Typical
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:6 RSECL Outputs, 20 ps max
2:1 MultiLevel Mux Inputs
160 ps Typical Propagation Delay
40 ps Typical Rise and Fall Times
Differential RSECL Outputs, 400 mV peaktopeak, typical
Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN32 Package, 5mm x 5mm
40C to +85C Ambient Operating Temperature
These Devices are PbFree and are RoHS Compliant
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 8 of
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
http://onsemi.com
32
1
NB7L
585R
AWLYYWWG
G
1
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
(Note: Microdot may be in either location)
50 W
IN1
VT1
IN1
50 W
IN0
VT0
IN0
Figure 1. Simplified Block Diagram
0
1
VREFAC1
VREFAC0
Q0
Q1
Q2
Q3
Q4
Q5
VCC
GND
+
SEL
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