参数资料
型号: NB7V586MMNG
厂商: ON Semiconductor
文件页数: 5/8页
文件大小: 0K
描述: IC CLK/DTA BUFF MUX TRNSLA 32QFN
标准包装: 74
系列: GigaComm™
类型: 扇出缓冲器(分配),多路复用器,变换器,数据
电路数: 1
比率 - 输入:输出: 2:6
差分 - 输入:输出: 是/是
输入: CML,LVDS,LVPECL
输出: CML
频率 - 最大: 6GHz
电源电压: 1.71 V ~ 1.89 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 管件
NB7V586M
http://onsemi.com
5
Table 6. AC CHARACTERISTICS VCC = 1.8 V $5%, VCCO1 = 1.2 V $5% or 1.8 V $5%, VCCO2 = 1.2 V $5% or 1.8 V $5%,
VCCO3 = 1.2 V $5% or 1.8 V $5%, GND = 0 V, TA = 40°C to 85°C (Note 11)
Symbol
Characteristic
Min
Typ
Max
Unit
fMAX
Maximum Input Clock Frequency, VOUTPP w 200 mV
4.0
6.0
GHz
fDATAMAX
Maximum Operating Input Data Rate (PRBS23)
10
Gbps
VOUTPP
Output Voltage Amplitude (See Figures 4, Note 15)
fin v 4.0 GHz
200
330
mV
tPLH, tPHL Propagation Delay to Output Differential @ 1 GHz,
INx/INx to Qn/Qn
Measured at Differential Crosspoint
SEL to Qn
125
175
250
300
ps
tPLH TC
Propagation Delay Temperature Coefficient
100
fs/°C
tSKEW
Output Output Skew (Within Device) (Note 12)
Device Device Skew (tpd Max tpdmin)
30
50
ps
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 4.0 GHz
45
50
55
%
tJITTER
Output Random Jitter (RJ) (Note 13)
fin v 4.0 GHz
Deterministic Jitter (DJ) (Note 14)
10 Gbps
0.2
0.8
10
ps rms
ps pkpk
VINPP
Input Voltage Swing (Differential Configuration) (Note 15)
100
1200
mV
tr, tf
Output Rise/Fall Times @ 1 GHz (20% 80%)
Qn, Qn
50
65
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV source, 50% duty cycle clock source. All outputs must be loaded with external 50 W to VCCOx. Input edge rates
40 ps (20% 80%).
12.Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from crosspoint of the inputs to the crosspoint of the outputs.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive PeaktoPeak data dependent jitter with input NRZ data at PRBS23.
15.Input and output voltage swing is a singleended measurement operating in differential mode.
Figure 2. Output Voltage Amplitude (VOUTPP) vs. Input
Frequency (fin) at Ambient Temperature (Typical)
fout, CLOCK OUTPUT FREQUENCY (GHz)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
Figure 3. Input Structure
50 W
VTx
VCC
INx
400
350
300
250
200
150
100
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
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