参数资料
| 型号： | NB7VQ1006MMNTXG |
| 厂商： | ON Semiconductor |
| 文件页数： | 1/10页 |
| 文件大小： | 0K |
| 描述： | IC EQUALIZER RECEIVER 24-QFN |
| 标准包装： | 3,000 |
| 逻辑类型： | 均衡器接收器 |
| 电源电压： | 1.71 V ~ 2.625 V |
| 位数： | 1 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 带卷 (TR) |
Semiconductor Components Industries, LLC, 2010
June, 2010 Rev. 2
1
Publication Order Number:
NB7VQ1006M/D
NB7VQ1006M
1.8V / 2.5V 10Gbps
Equalizer Receiver with 1:6
Differential CML Outputs
MultiLevel Inputs w/ Internal Termination
Description
The NB7VQ1006M is a high performance differential 1:6 CML
fanout buffer with a selectable Equalizer receiver. When placed in
series with a Data path operating up to 10 Gb/s, the NB7VQ1006M
will compensate the degraded data signal transmitted across a FR4
PCB backplane or cable interconnect and output six identical CML
copies of the input signal. Therefore, the serial data rate is increased by
reducing InterSymbol Interference (ISI) caused by losses in copper
interconnect or long cables.
The EQualizer ENable pin (EQEN) allows the IN/IN inputs to either
flow through or bypass the Equalizer section. Control of the Equalizer
function is realized by setting EQEN; When EQEN is set Low, the
IN/IN inputs bypass the Equalizer. When EQEN is set High, the IN/IN
inputs flow through the Equalizer. The default state at startup is LOW.
As such, the NB7VQ1006M is ideal for SONET, GigE, Fiber Channel,
Backplane and other Data distribution applications.
The differential inputs incorporate internal 50
W termination
resistors that are accessed through the VT pin. This feature allows the
NB7VQ1006M to accept various logic level standards, such as
LVPECL, CML or LVDS. This feature provides transmission line
termination at the receiver, eliminating external components. The
outputs have the flexibility of being powered by either a 1.8 V or 2.5 V
supply.
The NB7VQ1006M is a member of the GigaComm
family of high
performance Clock/Data products.
Features
Maximum Input Data Rate > 10 Gbps
Maximum Input Clock Frequency > 7.5 GHz
Backplane and Cable Interconnect Compensation
225 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV PeaktoPeak, Typical
Operating Range: VCC = 1.71 V to 2.625 V, GND = 0 V
Internal Input Termination Resistors, 50 W
QFN24 Package, 4 mm x 4 mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAM*
QFN24
MN SUFFIX
CASE 485L
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
NB7V
Q1006M
ALYWG
G
1
24
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
(Note: Microdot may be in either location)
EQ
SIMPLIFIED BLOCK DIAGRAM
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| NB7VQ572M | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:1.8V / 2.5V /3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator |
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