参数资料
| 型号： | NB7VQ58MMNG |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/9页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA MUX 2:1 7GHZ 16QFN |
| 标准包装： | 123 |
| 系列： | GigaComm™ |
| 类型： | 多路复用器，数据 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，LVDS，LVPECL |
| 输出： | CML |
| 频率 - 最大： | 7GHz |
| 电源电压： | 1.71 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（3x3） |
| 包装： | 管件 |
NB7VQ58M
http://onsemi.com
5
Symbol
Characteristic
Min
Typ
Max
Unit
fMAX
Maximum Input Clock Frequency
VOUTPP ≥ 200 mV
7
8
GHz
fDATAMAX Maximum Operating Data Rate (PRBS23)
10.7
12
Gbps
fSEL
Maximum Toggle Frequency, SEL
25
50
MHz
VOUTPP
Output Voltage Amplitude EQEN = 0 or 1
fin ≤ 7 GHz
200
400
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs,
@ 1 GHz, measured at differential crosspoint EQEN = 0 or 1
INn/INn to Q, Q
SEL to Q, Q
120
5
180
13
240
22
ps
ns
tPLH TC
Propagation Delay Temperature Coefficient
50
Dfs/°C
tskew
Device Device skew (tpdmax – tpdmin)
50
ps
tDC
Output Clock Duty Cycle
(Reference Duty Cycle = 50%)
fin v 5.0 GHz
fin v 7.0 GHz
45
40
50
55
60
%
tJITTER
RMS Random Clock Jitter (Note 13)
PeaktoPeak Data Dependent Jitter (Note 14)
fin v 7.0 GHz
fin v 10.7 Gbps
EQEN = 0 (v 3” FR4)
EQEN = 1 (12” FR4)
0.2
0.8
10
ps rms
ps pkpk
FN
Phase Noise, fc = 1 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
135
136
150
151
dBc
t∫FN
35
fs
Crosstalk Induced Jitter (Adjacent Channel) (Note 15)
0.7
ps RMS
VINPP
100
1200
mV
tr, tf
Output Rise/Fall Times @ 1 GHz (20% 80%)
Q, Q
15
35
50
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a VINPPmin source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps
(20% 80%).
12.Input and output voltage swings are singleended measurements operating in differential mode.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive PeaktoPeak data dependent jitter with input NRZ data at PRBS23 at 3 Gbps.
15.Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input
Frequency (fin) at Ambient Temperature (Typical)
fin, CLOCK INPUT FREQUENCY (GHz)
8
7
5
4
3
2
1
0
200
250
300
350
400
450
500
V
OUTP
P,
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
69
Figure 4. Typical Phase Noise
(VCC = 1.8 V, T = 255C, fc = 1 GHz)
10
155
150
145
140
135
130
125
120
115
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
FREQUENCY OFFSET (Hz)
POWER
(dBc)
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