参数资料
型号: NBSG16VSMNR2G
厂商: ON Semiconductor
文件页数: 13/14页
文件大小: 0K
描述: IC RCVR/DRIVER SIGE DIFF 16QFN
产品变化通告: Revision of Device Specifications 02/Oct/2008
标准包装: 3,000
类型: 收发器
应用: 仪表
安装类型: 表面贴装
封装/外壳: 16-VFQFN 裸露焊盘
供应商设备封装: 16-QFN(3x3)
包装: 带卷 (TR)
配用: NBSG16VSBAEVBOS-ND - BOARD EVAL BBG NBSG16VSBA
其它名称: NBSG16VSMNR2GOS
NBSG16VS
http://onsemi.com
8
Table 8. AC CHARACTERISTICS for FCBGA16 VCC = 0 V; VEE = 3.465 V to 3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 8) (Note 26)
10.7
(Note 29)
12
10.7
(Note 29)
12
10.7
(Note 29)
12
GHz
tPLH,
tPHL
Propagation Delay to Output Differen-
tial
(VCTRL = VCC 2 V) D → Q, Q
(VCTRL = VCC 1 V) D → Q, Q
100
125
120
145
140
100
125
120
145
140
100
125
120
145
140
ps
tSKEW
Duty Cycle Skew (Note 27)
3
10
3
10
3
10
ps
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
PeaktoPeak Data Dependent Jitter
fin < 10 Gb/s
0.8
TBD
2
0.8
TBD
2
0.8
TBD
2
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 28)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times (20% 80%)
@ 1 GHz
(VCTRL = VCC 2 V) Q, Q
(VCTRL = VCC 1 V) Q, Q
30
45
40
55
50
30
45
40
55
50
30
45
40
55
50
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
26.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC2.0 V. Input edge rates 40 ps (20% 80%).
27.tSKEW = |tPLHtPHL| for a nominal 50% differential clock input waveform. See Figure 10.
28.VINPP(MAX) cannot exceed VCC VEE (applicable only when VCC VEE t 2600 mV).
29.Conditions include input amplitude of 500 mV and VCTRL = VCC 2 V. Minimum output amplitude guarantee of 100 mV (see Output PP
Spec in Figure 8).
Table 9. AC CHARACTERISTICS for FCBGA16 VCC = 0 V; 3.0 V tVEE v 2.375 V or 2.375 V v VCC t 3.0 V; VEE = 0 V
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 9) (Note 30)
10.7
(Note 33)
12
10.7
(Note 33)
12
10.7
(Note 33)
12
GHz
tPLH,
tPHL
Propagation Delay to Output Differen-
tial
(VCTRL = VCC 2 V) D → Q, Q
(VCTRL = VCC 1 V) D → Q, Q
100
125
120
145
140
100
125
120
145
140
100
125
120
145
140
ps
tSKEW
Duty Cycle Skew (Note 31)
3
10
3
10
3
10
ps
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
PeaktoPeak Data Dependent Jitter
fin < 10 Gb/s
0.9
TBD
3
0.9
TBD
3
0.9
TBD
3
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 32)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times (20% 80%)
@ 1 GHz
(VCTRL = VCC 2 V) Q, Q
(VCTRL = VCC 1 V) Q, Q
25
22
50
45
70
60
25
22
50
45
70
60
25
22
50
45
70
60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
30.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC2.0 V. Input edge rates 40 ps (20% 80%).
31.tSKEW = |tPLHtPHL| for a nominal 50% differential clock input waveform. See Figure 10.
32.VINPP(MAX) cannot exceed VCC VEE (applicable only when VCC VEE t 2600 mV).
33.Conditions include input amplitude of 500 mV and VCTRL = VCC 2 V. Minimum output amplitude guarantee of 100 mV (see Output PP
Spec in Figure 9).
相关PDF资料
PDF描述
LFXP20C-4F388C IC FPGA 19.7KLUTS 268I/O 388-BGA
LFXP20C-3F388I IC FPGA 19.7KLUTS 268I/O 388-BGA
LFXP20E-4FN388C IC FPGA 19.7KLUTS 388FPBGA
LFXP20C-3FN388I IC FPGA 19.7KLUTS 388FPBGA
MIC5331-PNYMT TR IC REG LDO 3V/2.85V .3A 8TMLF
相关代理商/技术参数
参数描述
NBSG53A 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS
NBSG53A/D 制造商:未知厂家 制造商全称:未知厂家 功能描述:2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS
NBSG53A_06 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip−Flop/Clock Divider with Reset and OLS
NBSG53ABA 功能描述:触发器 2.5V/3.3V SiGe Diff RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel
NBSG53ABAEVB 功能描述:时钟和定时器开发工具 BBG NBSG53ABA EVAL BOARD RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V