参数资料
型号: NBXDDA016LN1TAG
厂商: ON Semiconductor
文件页数: 4/6页
文件大小: 0K
描述: IC CLK XO 133.33/137.03MHZ 6CLCC
产品培训模块: XO Replacement Overview
标准包装: 1
系列: PureEdge™
类型: 振荡器 - 晶体
频率: 133.33MHz,137.93MHz
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 70mA
工作温度: -40°C ~ 85°C
封装/外壳: 6-CLCC
包装: 标准包装
供应商设备封装: 6-CLCC(7x5)
安装类型: 表面贴装
其它名称: NBXDDA016LN1TAGOSDKR
NBXDDA016, NBXDDB016
http://onsemi.com
4
Table 7. AC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = 40°C to +85°C) (Note 3)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
fCLKOUT
Output Clock Frequency
FSEL = HIGH
137.93
MHz
FSEL = LOW
133.33
Df
Frequency Stability NBXDDB016
Frequency Stability NBXDDA016
(Note 4)
±20
±50
ppm
FNOISE
PhaseNoise Performance
100 Hz of Carrier
102
dBc/Hz
fCLKout = 133.33 MHz/137.93 MHz
(See Figures 3 and 4)
1 kHz of Carrier
120
dBc/Hz
10 kHz of Carrier
126
dBc/Hz
100 kHz of Carrier
126
dBc/Hz
1 MHz of Carrier
134
dBc/Hz
10 MHz of Carrier
162
dBc/Hz
tjit(F)
RMS Phase Jitter
12 kHz to 20 MHz
0.4
0.9
ps
tjitter
Cycle to Cycle, RMS
1000 Cycles
1.5
8
ps
Cycle to Cycle, PeaktoPeak
1000 Cycles
10
30
ps
Period, RMS
10,000 Cycles
0.8
4
ps
Period, PeaktoPeak
10,000 Cycles
7
20
ps
tOE/OD
Output Enable/Disable Time
200
ns
tDUTY_CYCLE
Output Clock Duty Cycle
(Measured at Cross Point)
48
50
52
%
tR
Output Rise Time (20% and 80%)
160
300
ps
tF
Output Fall Time (80% and 20%)
160
300
ps
tstart
Startup Time
1
5
ms
Aging
1st Year
3
ppm
Every Year After 1st
1
ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50 ohm to VDD. See Figure 5.
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
Figure 3. Typical Phase Noise Plot @ 133.33 MHz
Figure 4. Typical Phase Noise Plot @ 137.93 MHz
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