参数资料
型号: NC7SP05L6X
厂商: Fairchild Semiconductor
文件页数: 6/9页
文件大小: 0K
描述: IC INVERTER SGL ULP OD 6MICROPAK
产品变化通告: Die Material, Mold Compound Change 03/Oct/2008
标准包装: 5,000
系列: 7SP
逻辑类型: 逆变器,缓冲器
电路数: 1
输入数: 1
特点: 开路漏极
电源电压: 0.9 V ~ 3.6 V
电流 - 静态(最大值): 0.9µA
输出电流高,低: -,2.6mA
逻辑电平 - 低: 0.7 V ~ 0.9 V
逻辑电平 - 高: 1.6 V ~ 2.1 V
额定电压和最大 CL 时的最大传播延迟: 10ns @ 3V ~ 3.6V,30pF
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
供应商设备封装: Micro6?(TSOP-6)
封装/外壳: 6-UFDFN
包装: 带卷 (TR)
ICS8545I
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT / ICS LVDS FANOUT BUFFER
6
ICS8545BGI REV. B MARCH 02, 2009
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
SSB
Phas
e
Noise
dBc/Hz
Offset Frequency (Hz)
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